Superconducting phase-controlled hysteretic magnetic Josephson junction JMRAM memory cell

Patent metadata

Field	Value
Publication number	US-9520181-B1
Application number	US-201514854994-A
Country	US
Kind code	B1
Filing date	Sep 15, 2015
Priority date	Sep 15, 2015
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

One embodiment describes a JMRAM memory cell system. The system includes a phase hysteretic magnetic Josephson junction (PHMJJ) that stores one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state. The system also includes a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state. The system further includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.

First claim

What is claimed is:

1. A JMRAM memory cell comprising:
a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state;
a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state; and
at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.

2. The JMRAM memory cell of claim 1 , wherein the directional write element is configured as at least one transformer configured to inductively couple the read current from a primary winding to a secondary winding of the at least one transformer to provide the directional bias current through the PHMJJ in response to the read current during the data write operation.

3. The JMRAM memory cell of claim 1 , wherein the directional write element is configured as at least one transformer comprising a primary winding that is coupled to one of a bit-write line and a word-write line on which the write current is provided and a secondary winding that is coupled in series with the PHMJJ, the at least one transformer being configured to inductively couple the write current through the PHMJJ to provide the directional bias current to the PHMJJ in response to the write current during the data write operation.

4. The JMRAM memory cell of claim 1 , wherein the predetermined direction of the superconducting phase corresponds to a positive π-state of the PHMJJ with respect to the direction of the read current during the read operation.

5. The JMRAM memory cell of claim 1 , wherein the PHMJJ is configured to generate the superconducting phase in response to storing the first binary state, wherein the read current combines with a supercurrent produced via the superconducting phase of the PHMJJ to trigger the at least one Josephson junction to provide a first magnitude of a voltage at an output of the JMRAM memory cell, the first magnitude of the voltage being indicative of the first binary state.

6. The JMRAM memory cell of claim 5 , wherein the PHMJJ is configured to generate a zero superconducting phase in response to storing the other of the first and second binary states, wherein the combined read current and superconducting phase of the PHMJJ do not trigger the at least one Josephson junction, such that a second magnitude of the voltage is provided at the output, the second magnitude of the voltage being indicative of the other of the first and second binary states.

7. The JMRAM memory cell of claim 5 , wherein the at least one Josephson junction is arranged as a pair of Josephson junctions, wherein in response to the PHMJJ storing the first binary state, the read current triggers the pair of Josephson junctions in an oscillatory manner to provide the first magnitude of the voltage at the output.

8. A Josephson magnetic random access memory (JMRAM) system comprising an array of JMRAM memory cells comprising the JMRAM memory cell of claim 1 , the array of JMRAM memory cells being arranged in rows and columns, wherein the write current is a word-write current that is provided on a word-write line associated with a row of the array of JMRAM memory cells, wherein a second write current is provided on a bit-write line of the array of JMRAM memory cells as a bit-write current, wherein the read current is a word-read current that is provided on a word-read line associated with the row of the array of JMRAM memory cells, and wherein a second read current is provided on a bit-read line as a bit-read current.

9. The JMRAM of claim 8 , wherein each of the word-write line and the bit-write line associated with a given JMRAM memory cell are magnetically coupled to the PHMJJ, wherein the word-write current is provided on the word-write line through each of the JMRAM memory cells in a given one of the rows during the data write operation, and wherein the bit-write line comprises a plurality of bit-write lines that are each associated with a respective one of the columns.

10. The JMRAM of claim 8 , wherein the bit-read line comprises a plurality of bit-read lines that are each associated with a respective one of the columns, each of a respective plurality of bit-read currents being provided to the at least one Josephson junction associated with each of the respective JMRAM memory cells in a given one of the rows that is selected in response to the word-read current being provided during a data read operation to provide an indication of the stored digital state of each of the PHMJJs in the given one of the rows on the plurality of bit-read lines.

11. A method for writing a digital state to a JMRAM memory cell in a Josephson magnetic random access memory (JMRAM) system during a data write operation, the method comprising:
generating a word-write current on a word-write line to select a respective one of a plurality of rows of an array of JMRAM memory cells, each of the JMRAM memory cells comprising a phase hysteretic magnetic Josephson junction (PHMJJ) that is magnetically coupled to the word-write line and to a bit-write line and that is configured to store the digital state corresponding to one of a first binary state and a second binary state;
generating a bit-write current on the bit-write line associated with each of a plurality of columns of the array of JMRAM memory cells, the digital state of the PHMJJ being set in response to the word-write current and the bit-write current; and
generating a directional bias current through the PHMJJ in a predetermined direction during the data write operation to set the digital state of the PHMJJ in the first binary state, the directional bias current providing a superconducting phase of the PHMJJ corresponding to the first binary state.

12. The method of claim 11 , wherein generating the directional bias current comprises generating the directional bias current via at least one transformer.

13. The method of claim 12 , wherein generating the directional bias current via the at least one transformer comprises providing a read current through a primary winding of the at least one transformer, the primary winding being inductively coupled to a secondary winding of the at least one transformer, the secondary winding being coupled to PHMJJ, such that the at least one transformer induces the directional bias current through the PHMJJ in response to the read current during the data write operation.

14. The method of claim 12 , wherein generating the directional bias current via the at least one transformer comprises providing one of the word-write current and the bit-write current through a primary winding of the at least one transformer, the primary winding being inductively coupled to a secondary winding of the at least one transformer, the secondary winding being arranged in series with the PHMJJ, such that the at least one transformer induces the directional bias current through the PHMJJ in response to the respective one of the word-write current and the bit-write current during the data write operation.

15. The method of claim 11 , wherein generating the directional bias current comprises generating the directional bias current to set the PHMJJ in a positive π-state, such that a supercurrent produced

Assignees

• Miller Donald L
• Miklich Andrew Hostetler
• Herr Anna Y
• Herr Quentin P
• Reohr William Robert
• Northrop Grumman Systems Corp

Inventors

• Miller Donald L
• Miklich Andrew Hostetler
• Herr Anna Y
• Herr Quentin P
• Reohr William Robert

Classifications

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title