Package substrate

Patent metadata

Field	Value
Publication number	US-10412835-B2
Application number	US-201815953560-A
Country	US
Kind code	B2
Filing date	Apr 16, 2018
Priority date	Oct 29, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A package substrate includes a dielectric layer, a first circuit layer, a second circuit layer and at least one electrically conductive pole. The dielectric layer includes a first side and a second side opposite to the first side. The first circuit layer is located at the first side of the dielectric layer, and includes a plurality of spaced first circuit patterns embedded into the dielectric layer. The second circuit layer is located at the second side of the dielectric layer, and includes a plurality of spaced second circuit patterns located on the second side the dielectric layer. The electrically conductive pole electrically couples the first circuit layer to the second circuit layer. Each of the first circuit patterns has an extension direction from the first side toward the second side, and has widths gradually decreasing along the extension direction.

First claim

What is claimed is:

1. A package substrate comprising:
a dielectric layer comprising a first side and a second side, the second side opposite to the first side;
a first circuit layer located at the first side of the dielectric layer, and comprising a plurality of spaced first circuit patterns embedded into the dielectric layer;
a second circuit layer located at the second side of the dielectric layer, and comprising a plurality of spaced second circuit patterns located on the second side the dielectric layer;
at least one electrically conductive pole electrically coupling the first circuit layer to the second circuit layer; and
a solder resist film formed on a side of the first circuit layer facing away from the dielectric layer;
wherein each of the first circuit patterns has:
an extension direction from the first side of the dielectric layer toward the second side of the dielectric layer; and
widths gradually decreasing along the extension direction;

wherein the solder resist film defines a plurality of openings, and each of the openings has a width gradually decreasing along the extension direction.

2. The package substrate of claim 1 , wherein each of the first circuit patterns has a trapezoidal cross-section.

3. The package substrate of claim 2 , wherein each of the second circuit patterns has a trapezoidal cross-section.

4. The package substrate of claim 1 , wherein the at least one electrically conductive pole comprises a first end face and a second end face, the first end face and the second end at opposite ends of the at least one electrically conductive pole, the first end face connecting to the first circuit layer, and the second end face connecting to the second circuit layer.

5. The package substrate of claim 4 , wherein:
the first end face of the electrically conductive pole is in direct contact with the first circuit layer; and
the second end face being in direct contact with the second circuit layer.

6. The package substrate of claim 1 further comprising another solder resist film connecting to the second circuit layer.

7. The package substrate of claim 6 , wherein at least one of the second circuit patterns are exposed out of a corresponding solder resist film.

8. The package substrate of claim 6 , further comprising a chip electrically connected to the first circuit layer.

9. The package substrate of claim 8 , wherein the chip is connected to the first circuit patterns by a plurality of solder balls.

10. The package substrate of claim 8 , further comprising a molding compound layer:
covering the solder resist layer on the first circuit layer; and

surrounding the chip on the first circuit layer.

Assignees

• Qi Ding Tech Qinhuangdao Co Ltd
• Zhen Ding Tech Co Ltd

Inventors

• Huang Yu-Cheng

Classifications

• H05K3/20

  by affixing prefabricated conductor pattern {(H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence)} · CPC title

• H05K3/06 Primary

  the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K3/303

  with surface mounted components (H05K3/32 takes precedence) · CPC title

• H05K3/0038

  combined with laser drilling through a metal layer · CPC title