SRAM cell word line structure with reduced RC effects

Patent metadata

Field	Value
Publication number	US-10411019-B2
Application number	US-201615186446-A
Country	US
Kind code	B2
Filing date	Jun 18, 2016
Priority date	Oct 20, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

First claim

What is claimed is:

1. A device, comprising:
a memory bit cell;
at least one bit line disposed in a first metal layer and electrically coupled to the memory bit cell;
a word line disposed in a second metal layer above the first metal layer and electrically coupled to the memory bit cell;
a pair of metal islands disposed in the second metal layer at opposite sides of the word line and electrically coupled to a power supply, wherein the pair of metal islands each have a maximum width, and a maximum width of the word line is greater than the maximum width of each of the pair of metal islands; and
a pair of connection metal lines disposed in a third metal layer above the second metal layer and configured to electrically couple the pair of metal islands to the memory bit cell respectively, wherein the word line extends along a first direction, and the pair of connection metal lines extend along a second direction different from the first direction such that the pair of connection metal lines cross over the word line,
wherein the pair of connection metal lines do not overlap the at least one bit line in a layout view.

2. The device of claim 1 , wherein the word line comprises a zigzag shape.

3. The device of claim 1 , wherein the maximum width of the word line is 1.1 to 1.5 times wider than the maximum width of each of the pair of metal islands.

4. The device of claim 1 , wherein the at least one bit line comprises a pair of bit lines disposed in the first metal layer and electrically coupled to the memory bit cell, wherein the pair of connection metal lines do not overlap the pair of bit lines in the layout view.

5. The device of claim 4 , further comprising a power line disposed in the first metal layer and electrically coupled to the memory bit cell.

6. The device of claim 4 , wherein the pair of bit lines each extends along the second direction different from the first direction.

7. The device of claim 1 , wherein the memory bit cell is disposed in a column of a memory array, and each of the pair of metal islands is shared with a neighboring memory bit cell in a neighboring column of the memory array.

8. A device, comprising:
a memory bit cell;
at least one bit line disposed in a first metal layer and electrically coupled to the memory bit cell;
a first word line disposed in a second metal layer above the first metal layer and electrically coupled to the memory bit cell;
a pair of metal islands disposed in the second metal layer at opposite sides of the first word line and electrically coupled to a power supply;
a pair of first metal lines disposed in a third metal layer above the second metal layer, wherein one of the pair of first metal lines is configured to electrically couple only one of the pair of metal islands to the memory bit cell, wherein the first word line extends along a first direction, and the pair of first metal lines each extends along a second direction different from the first direction such that the pair of first metal lines each crosses over the first word line;
a second metal line disposed in the third metal layer; and
a second word line disposed in a fourth metal layer that covers the first word line, wherein the second word line is electrically coupled to the first word line through the second metal line,
wherein the pair of first metal lines do not overlap the at least one bit line in a layout view.

9. The device of claim 8 , wherein the second word line is overlapped with at least one portion of the pair of metal islands, and the one of the pair of first metal lines, which is configured to electrically couple the only one of the pair of metal islands to the memory bit cell, do not overlap an entire area of the only one of the pair of metal islands in the layout view.

10. The device of claim 8 , wherein the first word line comprises a zigzag shape.

11. The device of claim 8 , wherein the at least one bit line comprises a pair of bit lines disposed in the first metal layer and electrically coupled to the memory bit cell, wherein the pair of first metal lines do not overlap the pair of bit lines in the layout view.

12. The device of claim 11 , further comprising a power line disposed in the first metal layer and electrically coupled to the memory bit cell.

13. The device of claim 11 , wherein the pair of bit lines each extends along the second direction different from the first direction.

14. A method, comprising:
forming a memory bit cell;
forming at least one bit line disposed in a first metal layer and electrically coupled to the memory bit cell;
forming a first word line electrically coupled to the memory bit cell in a second metal layer above the first metal layer;
forming a pair of metal islands electrically coupled to a power supply at opposite sides of the first word line in the second metal layer, wherein the pair of metal islands each are formed with a maximum width, and a maximum width of the first word line is greater than the maximum width of each of the pair of metal islands; and
forming a pair of connection metal lines to electrically couple the pair of metal islands to the memory bit cell respectively in a third metal layer above the second metal layer, wherein the first word line extends along a first direction, and the pair of connection metal lines each extends along a second direction different from the first direction such that the pair of connection metal lines each crosses over the first word line,
wherein the pair of connection metal lines do not overlap the at least one bit line in a layout view.

15. The method of claim 14 , wherein forming the first word line comprises forming the first word line with a zigzag shape.

16. The method of claim 15 , wherein the maximum width of the first word line is 1.1 to 1.5 times wider than the maximum width of each of the pair of metal islands.

17. The method of claim 15 , wherein forming the at least one bit line disposed in the first metal layer and electrically coupled to the memory bit cell comprises forming a pair of bit lines electrically coupled to the memory bit cell in the first metal layer, wherein the pair of connection metal lines do not overlap the pair of bit lines in the layout view.

18. The method of claim 15 , further comprising forming a power line electrically coupled to the memory bit cell in the first metal layer.

19. The method of claim 14 , further comprising forming a second word line electrically coupled to the first word line in a fourth metal layer that fully covers the first word line.

20. The method of claim 14 , further comprising:
cutting two sides of each of the pair of metal islands by forming two cut metals that partially cover the two sides of each of the pair of metal islands; and
removing the cut metals,
wherein one of the pair of connection metal lines overlaps only a portion of only one of the pair of metal islands and does not overlap an entire area of the only one of the pair of metal islands in the layout view.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fujiwara Hidehiro
• Chan Wei-Min
• Lin Chih-Yu
• Chen Yen-Huei
• Liao Hung-Jen

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H01L23/5283

  Electricity · mapped topic

• H01L21/76838

  Electricity · mapped topic