Utilization of block-mask and cut-mask for forming metal routing in an IC device

Patent metadata

Field	Value
Publication number	US-9324722-B1
Application number	US-201514797757-A
Country	US
Kind code	B1
Filing date	Jul 13, 2015
Priority date	Jul 13, 2015
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask layer on an upper surface of a silicon-oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask; forming spacers on opposite sides of each mandrel, removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces; removing exposed sections of the hard-mask exposing sections of the silicon-oxide, removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask where the block-mask portions had been; removing the hard-mask through the cut-mask openings, removing the cut-mask; forming cavities in exposed regions of the silicon-oxide; removing the spacers and any remaining hard-mask; and forming metal lines in the cavities.

First claim

What is claimed is:

1. A method comprising:
forming a hard-mask layer on an upper surface of a silicon oxide layer;
forming spaced parallel mandrels on an upper surface of the hard-mask layer;
forming spacers on opposite sides of each mandrel and removing the mandrels, forming alternating mandrel and non-mandrel spaces;
forming block-mask portions over the mandrel and non-mandrel spaces, over the upper surface of the hard-mask layer;
removing exposed sections of the hard-mask layer exposing sections of an upper surface of the silicon oxide layer, and removing the block-mask portions;
forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask layer in areas where the block-mask portions had been;
removing the hard-mask layer through the cut-mask openings, and removing the cut-mask;
forming cavities in exposed regions of the silicon oxide layer;
removing the spacers and any remaining hard-mask layer; and
forming metal lines in the cavities.

2. The method of claim 1 , wherein forming the spacers comprises:
conformally forming a spacer material layer over the mandrels and the upper surface of the hard-mask layer; and
removing the spacer material layer from all horizontal surfaces.

3. The method of claim 1 , wherein the block-mask portions are wider and longer than the cut-mask openings.

4. The method of claim 1 , wherein a length of each block-mask portion equals a length of a metal line plus a width of a space between the metal line and an adjacent metal line on each side of the metal line.

5. The method of claim 4 , wherein a length of each cut-mask opening equals a length of a metal line.

6. The method of claim 1 , wherein tip-to-tip edges of adjacent cavities in the silicon oxide layer include smooth concave and convex tip edges.

7. The method of claim 1 , wherein the metal lines comprise a metal layer of a static random access memory device.

8. The method of claim 7 , wherein metal lines formed in the mandrel spaces comprise word lines.

9. The method of claim 1 , comprising forming adjacent block-mask portions in a tip-to-tip layout formation.

10. A method comprising:
forming a hard-mask on an upper surface of a silicon oxide layer;
forming a patterning template including a plurality of spaced parallel channels on an upper surface of the hard-mask, wherein the upper surface of the hard-mask is exposed between adjacent parallel channels;
forming block-mask portions over and extending in a same direction as a parallel channel, over the upper surface of the hard-mask layer;
removing exposed sections of the hard-mask layer exposing sections of an upper surface of the silicon oxide layer;
removing the block-mask portions and the patterning template;
forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask layer in areas where the block-mask portions had been;
removing the hard-mask layer through the cut-mask openings, and removing the cut-mask;
forming cavities in exposed regions of the silicon oxide layer; and
forming metal lines in the cavities.

11. The method of claim 10 , wherein forming the channels comprises:
forming spaced parallel dielectric lines on an upper surface of the hard-mask layer; and
forming spacers on opposite sides of each of the dielectric lines and removing the dielectric lines, forming alternating dielectric and non-dielectric spaces.

12. The method of claim 10 , wherein the block-mask portions are wider and longer than the cut-mask openings.

13. The method of claim 10 , wherein a length of each block-mask portion equals a length of a metal line plus a width of a space between the metal line and an adjacent metal line on each side of the metal line.

14. The method of claim 13 , wherein a length of each cut-mask opening equals a length of a metal line.

15. The method of claim 10 , wherein tip-to-tip edges of adjacent cavities in the silicon oxide layer include smooth concave and convex tip edges.

16. The method of claim 10 , wherein the metal lines comprise a metal layer of a static random access memory device.

17. The method of claim 11 , wherein metal lines formed in dielectric spaces comprise word lines.

18. The method of claim 10 , comprising forming adjacent block-mask portions in a tip-to-tip layout formation.

19. A method comprising:
forming a hard-mask layer on an upper surface of a silicon oxide layer;
forming spaced parallel mandrels on an upper surface of the hard-mask layer;
forming spacers on opposite sides of each mandrel and removing the mandrels, forming alternating mandrel and non-mandrel spaces;
forming block-mask portions over the mandrel and non-mandrel spaces, over the upper surface of the hard-mask layer, wherein adjacent block-mask portions are in a tip-to-tip layout formation;
removing exposed sections of the hard-mask layer exposing sections of an upper surface of the silicon oxide layer, and removing the block-mask portions;
forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask layer in areas where the block-mask portions had been, wherein the block-mask portions are wider and longer than the cut-mask openings;
removing the hard-mask layer through the cut-mask openings, and removing the cut-mask;
forming cavities in exposed regions of the silicon oxide layer, wherein tip-to-tip edges of adjacent cavities in the silicon oxide layer include smooth concave and convex tip edges;
removing the spacers and any remaining hard-mask layer; and
forming metal lines in the cavities, wherein the metal lines comprise a metal layer of a static random access memory device.

20. The method of claim 19 , wherein a length of each block-mask portion equals a length of a metal line plus a width of a space between the metal line and an adjacent metal line on each side of the metal line, and wherein a length of each cut-mask opening equals a length of a metal line.

Assignees

• Globalfoundries Inc

Inventors

• Woo Youngtag
• Yuan Lei
• Kye Jongwook

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/074 Primary

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H01L27/0207

  Electricity · mapped topic