Manufacturing process of element chip

Patent metadata

Field	Value
Publication number	US-10410924-B2
Application number	US-201815860827-A
Country	US
Kind code	B2
Filing date	Jan 3, 2018
Priority date	Jan 12, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.

First claim

What is claimed is:

1. A manufacturing process of an element chip, comprising:
a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions;
a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions; and
a dicing step for dicing the substrate along the apertures into a plurality of the element chips,
wherein the laser beam has a beam profile having a single M-shaped distribution extending over a whole width of the dicing regions, whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.

2. The manufacturing process according to claim 1 , wherein the semiconductor layer exposed by the apertures is etched by a first plasma exposure in the dicing step.

3. The manufacturing process according to claim 1 , wherein a spot shape of the laser beam is oval, elliptical or similar thereto, of which outline has a minor diameter corresponding to the width of the dicing regions.

4. The manufacturing process according to claim 1 , wherein a spot shape of the laser beam is a rectangular shape having a member extending along a direction of a width of the dicing regions, or a shape similar thereto.

5. The manufacturing process according to claim 1 , wherein a beam profile of the laser beam has a distribution selected from a group consisting of a Gaussian distribution and a top hat distribution along a longitudinal direction of the laser beam.

6. The manufacturing process according to claim 1 , wherein the laser beam is radiated two or more times to form the apertures in the dicing regions during the scribing step.

7. The manufacturing process according to claim 1 , further comprising a cleaning step for cleaning the apertures by a second plasma exposure after the scribing step, wherein the dicing step is implemented after the cleaning step.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Karasaki Hidehiko
• Saeki Hidefumi
• Harikai Atsushi

Classifications

• H10P72/0434

  mainly by convection · CPC title

• H10P72/0432

  mainly by conduction · CPC title

• H10P72/72

  using electrostatic chucks · CPC title

• H10P70/30

  Cleaning after the substrates have been singulated · CPC title

• H10P50/242

  of Group IV materials · CPC title