Hybrid wafer dicing approach using a rectangular shaped two-dimensional top hat laser beam profile or a linear shaped one-dimensional top hat laser beam profile laser scribing process and plasma etch process

Patent metadata

Field	Value
Publication number	US-9349648-B2
Application number	US-201414337810-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Jul 22, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

First claim

What is claimed is:

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the rectangular shaped two-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

2. The method of claim 1 , wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises using a femto-second based rectangular shaped two-dimensional top hat beam.

3. The method of claim 1 , wherein patterning the mask with the laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.

4. The method of claim 3 , wherein each of the trenches has a width, and wherein each of the corresponding trench extensions has the width.

5. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a linear shaped one-dimensional top hat beam, wherein scribing with the laser beam having the linear shaped one-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the linear shaped one-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

6. The method of claim 5 , wherein scribing with the laser beam having the linear shaped one-dimensional top hat beam comprises using a femto-second based linear shaped one-dimensional top hat beam.

7. The method of claim 5 , wherein patterning the mask with the laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.

8. The method of claim 7 , wherein each of the trenches has a width, and wherein each of the corresponding trench extensions has the width.

9. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam or with a laser beam having a linear shaped one-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

10. The method of claim 9 , wherein scribing with the laser beam having the top hat laser beam profile comprises using a femto-second based top hat laser beam.

11. The method of claim 1 , wherein cleaning the exposed regions of the semiconductor wafer with a plasma process comprises cleaning the exposed regions of the semiconductor wafer with a reactive plasma-based cleaning process.

12. The method of claim 5 , wherein cleaning the exposed regions of the semiconductor wafer with a plasma process comprises cleaning the exposed regions of the semiconductor wafer with a reactive plasma-based cleaning process.

13. The method of claim 9 , wherein cleaning the exposed regions of the semiconductor wafer with a plasma process comprises cleaning the exposed regions of the semiconductor wafer with a reactive plasma-based cleaning process.

Assignees

• Lei Wei-Sheng
• Kumar Prabhat
• Park Jungrae
• Eaton Brad
• Kumar Ajay
• Applied Materials Inc

Inventors

• Lei Wei-Sheng
• Kumar Prabhat
• Park Jungrae
• Eaton Brad
• Kumar Ajay

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title