Semiconductor devices including insulating capping structures

Patent metadata

Field	Value
Publication number	US-10403640-B2
Application number	US-201815933062-A
Country	US
Kind code	B2
Filing date	Mar 22, 2018
Priority date	Sep 4, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of vertically stacked gate electrodes on a substrate;
an insulating capping structure on the plurality of gate electrodes, the insulating capping structure including a first upper surface and a second upper surface, a first distance between the first upper surface and a top surface of the substrate being greater than a second distance between the second upper surface and the top surface of the substrate, and the first upper surface not overlying the second upper surface;
a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure, the memory cell vertical structure being laterally spaced apart from the second upper surface; and
a bit line electrically connected to the memory cell vertical structure.

2. The semiconductor device of claim 1 , wherein the insulating capping structure comprises a first insulating capping pattern comprising the first upper surface, and a second insulating capping pattern comprising the second upper surface.

3. The semiconductor device of claim 1 , wherein the memory cell vertical structure comprises a channel semiconductor layer extending in a direction perpendicular to the top surface of the substrate, and a dielectric structure between the channel semiconductor layer and the plurality of gate electrodes.

4. The semiconductor device of claim 1 , further comprising an upper insulating layer on the insulating capping structure,
wherein the memory cell vertical structure extends in a direction perpendicular to the top surface of the substrate to pass through the upper insulating layer.

5. The semiconductor device of claim 1 ,
wherein the plurality of gate electrodes are sequentially stacked in a memory cell array region of the substrate,
wherein the plurality of gate electrodes comprises a lower gate electrode, a plurality of intermediate gate electrodes on the lower gate electrode, and an upper gate electrode on the plurality of intermediate gate electrodes,
wherein the plurality of gate electrodes comprise pad regions extending from the memory cell array region to a connection region of the substrate, the pad regions being arranged to have a stepped shape, and
wherein the pad regions of the plurality of gate electrodes comprise an upper pad region of the upper gate electrode, intermediate pad regions of the plurality of intermediate gate electrodes, and a lower pad region of the lower gate electrode.

6. The semiconductor device of claim 2 , wherein the first insulating capping pattern comprises a first oxide and the second insulating capping pattern comprises a second oxide, the second oxide being more porous than the first oxide and/or having a density lower than a density of the first oxide.

7. The semiconductor device of claim 3 , wherein a difference between the first distance between the first upper surface and the top surface of the substrate and the second distance between the second upper surface and the top surface of the substrate is less than a thickness of the dielectric structure.

8. The semiconductor device of claim 3 , further comprising: a gate dielectric between one of the plurality of gate electrodes and the memory cell vertical structure,
wherein a difference between the first distance between the first upper surface and the top surface of the substrate and the second distance between the second upper surface and the top surface of the substrate is less than a thickness of the gate dielectric.

9. The semiconductor device of claim 5 ,
wherein the first upper surface of the insulating capping structure overlaps the plurality of gate electrodes in the memory cell array region, and overlaps the upper pad region of the upper gate electrode, and
wherein the second upper surface of the insulating capping structure overlaps the intermediate pad regions and the lower pad region in the connection region.

10. The semiconductor device of claim 9 , further comprising:
an upper gate contact plug passing through the first upper surface of the insulating capping structure, electrically connected to the upper pad region, and spaced apart from the second upper surface of the insulating capping structure; and
intermediate gate contact plugs passing through the second upper surface of the insulating capping structure, electrically connected to the intermediate pad regions, and spaced apart from the first upper surface of the insulating capping structure,
wherein a boundary between the first upper surface and the second upper surface of the insulating capping structure is between the intermediate gate contact plugs and the upper gate contact plug.

11. A semiconductor device, comprising:
a plurality of gate electrodes on a substrate;
an insulating capping structure on the plurality of gate electrodes, the insulating capping structure including a first surface layer and a second surface layer that is thicker than the first surface layer, and the first surface layer not overlying the second surface layer;
a channel hole passing through the plurality of gate electrodes and the insulating capping structure, passing through the first surface layer, and spaced apart from the second surface layer; and
a channel semiconductor layer within the channel hole, the channel semiconductor layer extending in a direction perpendicular to a top surface of the substrate,
wherein the insulating capping structure comprises a first insulating capping pattern including the first surface layer, and a second insulating capping pattern including the second surface layer,
wherein a thickness of the first surface layer of the first insulating capping pattern is less than a thickness of a remainder of the first insulating capping pattern, and
wherein a thickness of the second surface layer of the second insulating capping pattern is less than a thickness of a remainder of the second insulating capping pattern.

12. The semiconductor device of claim 11 ,
wherein the substrate includes a memory cell array region and a connection region,
wherein the plurality of gate electrodes are in the memory cell array region of the substrate and comprise pad regions extending to the connection region of the substrate, the pad regions being formed in the connection region to have a stepped shape,
wherein the plurality of gate electrodes comprises a lower gate electrode, a plurality of intermediate gate electrodes on the lower gate electrode, and an upper gate electrode on the plurality of intermediate gate electrodes, and
wherein the pad regions comprise an upper pad region of the upper gate electrode, intermediate pad regions of the plurality of intermediate gate electrodes, and a lower pad region of the lower gate electrode.

13. The semiconductor device of claim 11 , wherein the insulating capping structure includes a first upper surface and a second upper surface, and
wherein a first distance between the first upper surface and the top surface of the substrate is greater than a second distance between the second upper surface and the top surface of the substrate.

14. The semiconductor device of claim 12 , wherein the first surface layer overlaps the upper gate electrode and the upper pad region, and
the second surface layer overlaps the intermediate pad regions and the lower pad region.

15. The semiconductor device of claim 12 , further comprising:
an upper gate contact plug passing through the first surface layer of the insulating capping structure, electrically connected to the upper pad region, and spaced apart from the second surface layer;

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Chang Sun
• Park Ki Chul
• Pyon Young Beom
• Kwon Byoung Ho
• Yoon Bo Un

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H01L23/535

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic