Hybrid bonding materials comprising ball grid arrays and metal inverse opal bonding layers, and power electronics assemblies incorporating the same

Patent metadata

Field	Value
Publication number	US-10403594-B2
Application number	US-201815876929-A
Country	US
Kind code	B2
Filing date	Jan 22, 2018
Priority date	Jan 22, 2018
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.

First claim

What is claimed is:

1. A hybrid bonding layer comprising:
a metal inverse opal (MIO) layer; and
a ball grid array (BGA) disposed within the MIO layer.

2. The hybrid bonding layer of claim 1 , wherein the MIO layer comprises a copper metal inverse opal (CIO) layer.

3. The hybrid bonding layer of claim 1 , wherein the BGA comprises a plurality of balls formed from at least one of aluminum, nickel, copper, manganese, and alloys thereof.

4. The hybrid bonding layer of claim 1 , wherein the BGA comprises a plurality of balls disposed in the MIO layer uniformly or non-uniformly.

5. The hybrid bonding layer of claim 1 , wherein the BGA comprises a plurality of core-shell balls with a core formed from at least one of aluminum, nickel, copper, manganese, and alloys thereof, and a shell formed from at least one of aluminum, nickel, copper, manganese, tin, and alloys thereof.

6. The hybrid bonding layer of claim 5 , wherein the shell is formed from tin and alloys thereof.

7. The hybrid bonding layer of claim 1 , further comprising a pair of low melting point bond layers, wherein the MIO layer and the BGA disposed within the MIO layer are positioned between the pair of low melting point bond layers.

8. The hybrid bonding layer of claim 7 , wherein the pair of low melting point bond layers comprise a melting point below a TLP sintering temperature and the MIO layer and the BGA each have a melting point above the TLP sintering temperature.

9. The hybrid bonding layer of claim 8 , wherein the pair of low melting point bond layers are formed from tin and alloys thereof.

10. A power electronics assembly comprising:
a substrate;
a semiconductor device; and
a hybrid bonding layer disposed between and bonded to the semiconductor device and the substrate, the hybrid bonding layer comprising a metal inverse opal (MIO) layer and a ball grid array (BGA) disposed within the MIO layer.

11. The power electronics assembly of claim 10 , wherein the MIO layer comprises a copper metal inverse opal (CIO) layer.

12. The power electronics assembly of claim 10 , wherein the BGA comprises a plurality of balls formed from at least one of aluminum, nickel, copper, manganese, and alloys thereof.

13. The power electronics assembly of claim 12 , further comprising an intermetallic layer between the MIO layer and at least one of the plurality of balls.

14. The power electronics assembly of claim 12 , wherein the plurality of balls are disposed in the MIO layer uniformly or non-uniformly.

15. The power electronics assembly of claim 12 , further comprising a cooling fluid flowing within the hybrid bonding layer, wherein the plurality of balls are configured to transfer heat from the substrate to the cooling fluid.

16. The power electronics assembly of claim 10 , further comprising a first intermetallic layer between the hybrid bonding layer and the substrate and a second intermetallic layer between the hybrid bonding layer and the semiconductor device.

17. A process for manufacturing a power electronics assembly comprising:
positioning a hybrid bonding layer between a substrate and a semiconductor device to provide a substrate/semiconductor device assembly, the hybrid bonding layer comprising a metal inverse opal (MIO) layer and a ball grid array (BGA) disposed within the MIO layer;
heating the substrate/semiconductor device assembly to a transient liquid phase (TLP) sintering temperature between about 280° C. and 350° C. and TLP bonding the hybrid bonding layer between and to the substrate and the semiconductor device; and
cooling the substrate/semiconductor device assembly from the TLP sintering temperature to ambient temperature.

18. The process of claim 17 , wherein the BGA comprises a plurality of balls and the MIO layer is formed around the plurality of balls.

19. The process of claim 17 , further comprising forming the MIO layer with a plurality of hollow spaces for the BGA to be positioned within and positioning the BGA within the plurality of hollow spaces to form the hybrid bonding layer.

20. The process of claim 17 , wherein:
the hybrid bonding layer is positioned between a pair of low melting point bond layers;
the pair of low melting point bond layers have a melting point less than 280° C.; and
the pair of low melting point bond layers at least partially melt and isothermally solidify during heating of the substrate/semiconductor device assembly to the TLP sintering temperature.

Assignees

• Toyota Eng & Mfg North America

Inventors

• Joshi Shailesh N
• Dede Ercan Mehmet

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/07331

  Connecting techniques · CPC title