Package on package bonding structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9673182-B2
Application number	US-201615204844-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Dec 28, 2012
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.

First claim

What is claimed is:

1. A method of forming a package on package (PoP) structure comprising:
forming a first die package, comprising:
attaching a metal ball with a convex surface to a first contact pad on a substrate;
applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste, wherein the distal end is a furthest end of the metal ball from the substrate;
attaching a semiconductor die to the substrate; and
forming a molding compound between the semiconductor die and the metal ball, wherein the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound; and

bonding an external connector of a second die package to the solder paste layer of the first die package.

2. The method of claim 1 , wherein the solder paste layer has a first width at an interface between the solder paste layer and the molding compound, and a second width for the second portion of the solder paste layer, wherein the first width is smaller than the second width.

3. The method of claim 1 , wherein the attaching the semiconductor die comprises performing a reflow process, wherein the reflow process modifies a profile of the solder paste layer disposed over the distal end of the metal ball.

4. The method of claim 1 , further comprising forming an underfill before the forming of the molding compound, wherein the underfill fills a gap between the semiconductor die and the substrate.

5. The method of claim 1 , wherein the forming of the molding compound comprises forming the molding compound using a molded underfill (MUF), wherein the MUF fills a gap between the semiconductor die and the substrate.

6. The method of claim 1 , wherein the upper surface of the molding compound extends further away from the substrate than the metal ball.

7. The method of claim 6 , wherein a distance between a top surface of the metal ball and the upper surface of the molding compound is between about 150 μm to about 200 μm.

8. The method of claim 1 , further comprising forming a first intermetallic compound (IMC) layer between the solder paste layer and the metal ball, the first IMC layer having a thickness in a range from about 2 μm to about 5 μm.

9. The method of claim 8 , further comprising forming a second IMC layer between the metal ball and the first contact pad, the second IMC layer having a thickness in a range from about 3 μm to about 8 μm.

10. The method of claim 1 , wherein the bonding of the external connector of the second die package to the solder paste layer of the first die package comprises performing a reflow process to merge a solder region of the external connector of the second die package with the solder paste layer of the first die package.

11. The method of claim 10 , further comprising forming a bonding layer over the first contact pad prior to the attaching of the metal ball.

12. The method of claim 1 , wherein a top surface of the solder paste layer is about 150 μm to about 200 μm above the upper surface of the molding compound.

13. A method of forming a package on package (PoP) structure comprising:
forming a first external connector on a substrate, comprising:
bonding a metal ball with a convex surface to a first contact pad of the substrate; and
depositing a solder paste layer on an upper portion of the metal ball distal the substrate;

attaching a first semiconductor die to the substrate, wherein the first external connector and the first semiconductor die are electrically coupled to interconnect structures in the substrate;
forming a molding compound around the first external connector and the first semiconductor die; and
attaching a second die package to the first external connector by forming a bonded solder layer between a second contact pad on the second die package and the metal ball, wherein the bonded solder layer extends below an upper surface of the molding compound distal the substrate, wherein the bonded solder layer has a first portion between the second die package and the upper surface of the molding compound and a second portion between the upper surface of the molding compound and the substrate, wherein a width of the second portion of the bonded solder layer increases monotonically from the upper surface of the molding compound to a lower portion of the second portion closest to the substrate.

14. The method of claim 13 , wherein the upper surface of the molding compound extends further away from the substrate than a top surface of the metal ball distal the substrate.

15. The method of claim 13 , further comprising forming a second external connector comprising solder or solder alloy on the second contact pad before the attaching the second die package.

16. The method of claim 13 , wherein the solder paste layer has a first portion above the upper surface of the molding compound, and has a second portion under the upper surface of the molding compound.

17. A method of forming a package on package (PoP) structure comprising:
forming a first die package, comprising:
attaching a semiconductor die to a first side of a substrate;
attaching a metal ball with a convex surface to a first contact pad of the substrate, the first contact pad being on the first side of the substrate; and
forming a molding compound over the first side of the substrate, the molding compound interposed between the semiconductor die and the metal ball, an upper surface of the molding compound extending further away from the substrate than an upper surface of the metal ball; and

bonding a second die package having a second contact pad to the first die package via a bonded solder layer between the second contact pad of the second die package and the metal ball of the first die package, the bonded solder layer contacting the molding compound and extending below the upper surface of the molding compound, the bonded solder layer having a first width at the upper surface of the molding compound and a second width below the upper surface of the molding compound, the second width continuously increasing from the upper surface of the molding compound to a lowest portion of the bonded solder layer disposed under the upper surface of the molding compound.

18. The method of claim 17 , further comprising forming a bonding layer on the first contact pad before the attaching the metal ball.

19. The method of claim 17 , wherein the bonding of the second die package comprises performing a reflow process, the reflow process merging a solder region of an external connector of the second die package with a solder paste layer of the first die package.

20. The method of claim 17 , wherein the forming of the first die package further comprises forming a solder paste layer over the metal ball, wherein a first portion of the solder paste layer extends above the upper surface of the molding compound, and a second portion of the solder paste layer extends below the upper surface of the molding compound.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Kuei-Wei
• Chen Wei-Yu
• Chen Meng-Tse
• Lin Wei-Hung
• Cheng Ming-Da
• Liu Chung-Shi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title