Process-induced distortion prediction and feedforward and feedback correction of overlay errors

Patent metadata

Field	Value
Publication number	US-10401279-B2
Application number	US-201414490408-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Oct 29, 2013
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.

First claim

What is claimed is:

1. A method, comprising:
obtaining a first set of wafer geometry measurements of a wafer prior to the wafer undergoing a fabrication process;
obtaining a second set of wafer geometry measurements of the wafer after the wafer undergoes the fabrication process;
calculating an initial film force distribution on the wafer based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
calculating an additional film force distribution on the wafer at least partially based on the initial film force distribution;
utilizing a finite element (FE) model to estimate a process-induced distortion of the wafer, wherein the FE model is utilized at least partially based on at least one of the initial film force distribution or the additional film force distribution; and
adjusting one or more process tools of a semiconductor fabrication facility based on the estimated process-induced distortion, wherein the one or more process tools of the semiconductor fabrication facility include a first process tool implemented to fabricate the wafer, wherein the estimated process-induced distortion is provided to the first process tool via a feedback loop.

2. The method of claim 1 , wherein the initial film force distribution is calculated as a product of a film stress and a film thickness.

3. The method of claim 2 , wherein the film stress is determined at least partially based on the first set of wafer geometry measurements and the second set of wafer geometry measurements.

4. The method of claim 1 , wherein the FE model is configured for:
generating a wafer model to represent at least one of one or more mechanical properties or a geometry of the wafer;
simulating one or more effects of the at least one of the initial film force distribution or the additional film force distribution on the wafer model; and
calculating one or more out-of-plane distortions (OPD) based on the generated wafer model with the one or more simulated effects of the at least one of the initial film force distribution or the additional film force distribution.

5. The method of claim 1 , wherein the FE model is configured for:
generating a wafer model to represent at least one of one or more mechanical properties or a geometry of the wafer;
simulating one or more effects of the at least one of the initial film force distribution or the additional film force distribution on the wafer model;
simulating one or more effects of wafer chucking on the wafer model; and
calculating one or more in-plane distortions (IPD) based on the wafer model with the one or more simulated effects of the one or more simulated effects of wafer chucking and the at least one of the initial film force distribution or the additional film force distribution.

6. The method of claim 1 , wherein the one or more process tools of the semiconductor fabrication facility include a second process tool, wherein the estimated process-induced distortion is provided to the second process tool via a feed forward loop, wherein the second process tool is adjustable via the estimated process-induced distortion.

7. The method of claim 1 , wherein the calculating the additional film force distribution on the wafer at least partially based on the initial film force distribution comprises:
calculating a change in shape of the wafer based on the initial film force distribution and at least one of one or more calculated mechanical properties or a calculated geometry of the wafer; and
comparing the calculated change in shape of the wafer against a measured change in shape of the wafer,
wherein the calculate and compare processes are iteratively performed until a difference between the calculated change in shape of the wafer and the measured change in shape of the wafer is below a predetermined threshold.

8. The method of claim 1 , further comprising:
obtaining a third set of wafer geometry measurements of the wafer after at least a second fabrication process;
calculating a second initial film force distribution on the wafer based on the second set of wafer geometry measurements and the third set of wafer geometry measurements; and
utilizing the FE model to estimate at least a second process-induced distortion of the wafer, wherein the FE model is utilized at least partially based on the second initial film force distribution.

9. A method, comprising:
generating one or more basis film force distribution maps for a wafer;
performing finite element (FE) model based overlay error prediction for the one or more basis film force distribution maps, wherein the performing the FE model based overlay error prediction generates an overlay error prediction for the one or more basis film force distribution maps;
storing the one or more generated basis film force distribution maps;
storing the overlay error prediction generated for the stored one or more generated basis film force distribution maps;
forming a complete overlay error map of the wafer by:
synthesizing the overlay error prediction based on the one or more basis film force distribution maps to generate one or more overlay error contributions; and
combining one or more overlay error contributions; and

adjusting one or more process tools of a semiconductor fabrication facility based on the complete overlay error map, wherein the one or more process tools of the semiconductor fabrication facility include a first process tool implemented to fabricate the wafer, wherein the complete overlay error map is provided to the first process tool via a feedback loop.

10. The method of claim 9 , wherein at least one of the generating the one or more basis film force distribution maps, the performing the FE model based overlay error prediction for the one or more basis film force distribution maps, the storing the one or more basis film force distribution maps, and the storing the overlay error prediction generated for the stored one or more basis film force distribution maps are part of an off-line training process, and are performed prior to and independently from the forming the complete overlay error map of the wafer.

11. The method of claim 9 , wherein the one or more basis film force distribution maps includes at least one of one or more Zernike basis film force distribution maps or one or more Cosine basis film force distribution maps, wherein the at least some of the basis film force distribution maps of the one or more basis film force distribution maps include an image representing a film force distribution.

12. The method of claim 9 , wherein the forming the complete overlay error map of the wafer comprises:
obtaining a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process;
obtaining a second set of wafer geometry measurements of the wafer after the wafer undergoes the fabrication process;
calculating a film force distribution of the wafer based on the first set of wafer geometry measurements and the second set of wafer geometry measurements;
decomposing the film force distribution of the wafer to a linear combination of one or more basis film force distribution maps; and
synthesizing the generated overlay error prediction for the one or more basis film force distribution maps in the linear combination.

13. The method of claim 12 , wherein the film force is calculated as a product of a film stress and a film thickness.

14. The method of claim 13 , wherein the film stress is determined at least partially based on the first set of wafer geometry measurements and the second set of wafer geometry measurements.

15. The method of claim 9

Assignees

• Kla Tencor Corp

Inventors

• Vukkadala Pradeep
• Chen Haiguang
• Sinha Jaydeep
• Veeraraghavan Sathish

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G03F7/70783

  Handling stress or warp of chucks, masks or workpieces, e.g. to compensate for imaging errors or considerations related to warpage of masks or workpieces due to their own weight · CPC title

• G03F7/705

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G01L5/0047

  measuring forces due to residual stresses · CPC title