Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin

Patent metadata

Field	Value
Publication number	US-9704864-B2
Application number	US-201514746229-A
Country	US
Kind code	B2
Filing date	Jun 22, 2015
Priority date	Aug 11, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin on a substrate and extending in a first direction;
first and second transistors on the fin and spaced apart from each other in the first direction;
a first isolation layer in the fin between the first and second transistors, the first isolation layer extending in a second direction intersecting the first direction and isolating the first and second transistors from each other; and
a second isolation layer on the first isolation layer and extending in the second direction,
wherein the second isolation layer comprises first and second regions comprising different first and second widths, respectively, and
wherein a third width, in the fin, of the first isolation layer is narrower than a fourth width of a protruding portion of the fin.

2. The semiconductor device of claim 1 ,
wherein the first region of the second isolation layer is on a top portion of the second region of the second isolation layer,
wherein the first width of the first region of the second isolation layer is wider than the second width of the second region of the second isolation layer, and
wherein the third width of the first isolation layer is narrower than the first and second widths of the second isolation layer.

3. The semiconductor device of claim 1 , wherein the third width of the first isolation layer is narrower than the first and second widths of the second isolation layer.

4. The semiconductor device of claim 3 , further comprising:
first and second inner spacers on first and second side surfaces, respectively, of the first isolation layer; and
first and second dummy spacers on third and fourth side surfaces of the first and second inner spacers, respectively,
wherein the inner spacers and the dummy spacers comprise different materials, respectively.

5. The semiconductor device of claim 4 ,
wherein each of the dummy spacers comprises a third region and a fourth region,
wherein the third and fourth regions comprise different fifth and sixth widths, respectively,
wherein the third region overlaps a portion of the fourth region, and
wherein the fifth width of the third region is narrower than the sixth width of the fourth region.

6. The semiconductor device of claim 1 , wherein the first and second isolation layers comprise a nitride layer and an oxide layer, respectively.

7. The semiconductor device of claim 6 ,
wherein the oxide layer of the second isolation layer comprises a first oxide layer, and
wherein the first isolation layer comprises a second oxide layer upwardly extending along side surfaces of the nitride layer of the first isolation layer.

8. The semiconductor device of claim 7 ,
wherein the second isolation layer further comprises a third region comprising a fifth width that is different from the first and second widths of the first and second regions,
wherein the third region underlies the second region, and
wherein the fifth width of the third region is narrower than the second width of the second region.

9. The semiconductor device of claim 6 ,
wherein the oxide layer of the second isolation layer comprises a first oxide layer,
wherein the first isolation layer comprises a second oxide layer, and
wherein the nitride layer of the first isolation layer upwardly extends along side surfaces of the second oxide layer of the first isolation layer.

10. The semiconductor device of claim 1 ,
wherein the first isolation layer and the second isolation layer comprise the same material, and
wherein the semiconductor device further comprises a gap within the second isolation layer.

11. The semiconductor device of claim 1 , further comprising a protection layer on the second isolation layer and comprising a nitride layer.

12. The semiconductor device of claim 1 , wherein the first isolation layer protrudes from within the fin beyond an uppermost surface of the fin.

13. A semiconductor device comprising:
a substrate comprising first and second regions;
a first fin in the first region and extending in a first direction;
first and second transistors on the first fin and spaced apart from each other in the first direction;
a first isolation layer in the first fin between the first and second transistors and extending in a second direction intersecting the first direction, the first isolation layer isolating the first and second transistors from each other;
a second fin in the second region and extending in the first direction;
third and fourth transistors on the second fin and spaced apart from each other in the first direction; and
a second isolation layer in the second fin between the third and fourth transistors and extending in the second direction, the second isolation layer isolating the third and fourth transistors from each other,
wherein the first isolation layer comprises first and second regions thereof comprising different first and second widths, respectively, and
wherein the first isolation layer and the second isolation layer comprise different materials, respectively.

14. The semiconductor device of claim 13 ,
wherein the first and second regions of the substrate comprise a PMOS region and an NMOS region, respectively, and
wherein the first and second isolation layers comprise a tensile stress material and a compressive stress material, respectively.

15. A semiconductor device comprising:
a fin protruding from a substrate;
first and second gate structures on the fin;
a first source or drain region and a second source or drain region on the fin between the first and second gate structures; and
a non-uniformly-wide isolation region comprising:
a first portion thereof in a recess region of the fin that is between and spaced apart from the first source or drain region and the second source or drain region; and
a second portion thereof that overlaps the first portion of the non-uniformly-wide isolation region and extends laterally to overlap an upper surface of the fin, the second portion of the non-uniformly-wide isolation region comprising a first width that is wider than a second width, in the recess region of the fin, of the first portion of the non-uniformly-wide isolation region,

wherein the second width, in the recess region of the fin, of the first portion of the non-uniformly-wide isolation region is narrower than a third width of a protruding portion of the fin.

16. The semiconductor device of claim 15 ,
wherein the first and second portions of the non-uniformly-wide isolation region comprise first and second isolation layers, respectively, comprising different respective materials, and
wherein the second isolation layer comprises a non-uniformly-wide isolation layer comprising:
the first width; and
a fourth width that is wider than the second width and unequal to the first width.

17. The semiconductor device of claim 16 , further comprising a spacer on the fin, the spacer comprising a first portion thereof that is recessed such that a second portion of the spacer protrudes beyond the first portion of the spacer to extend along a side surface of the non-uniformly-wide isolation layer.

18. The semiconductor device of claim 17 ,
wherein the spacer comprises a first spacer, and
wherein the semiconductor device further comprises:
a second spacer between the first spacer and the first isolation layer;
a protection layer on the second isolation layer; and
a gap within the second isolation layer.

19. The semiconductor device of claim 15 , wherein:
the substrate comprises first and second regions;

Assignees

• Park Sang-Jine
• Yoon Bo-Un
• Jeon Ha-Young
• Gil Yeon-Jin
• Yun Ji-Won
• Choi Won-Sang
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Jine
• Yoon Bo-Un
• Jeon Ha-Young
• Gil Yeon-Jin
• Yun Ji-Won
• Choi Won-Sang

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title