Fin field-effect transistor and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2017200810-A1
Application number	US-201715398786-A
Country	US
Kind code	A1
Filing date	Jan 5, 2017
Priority date	Jan 7, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

The present disclosure provides fin field-effect transistors and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a first region and a second region; forming first fins in the first region and second fins in the second region; forming a liner oxide layer on side surfaces of the first fins, the second fins and a surface of the substrate; forming an insulating barrier layer on the liner oxide layer in the first region; forming a precursor material layer on the insulating barrier layer in the first region and on the liner oxide layer in the second region; performing a curing annealing process to convert the precursor material into an insulation layer; and removing a top portion of the insulation layer to form an isolating layer and removing portions of the liner oxide layer, the insulating barrier layer, the first oxide layer and the second oxide layer.

First claim

What is claimed is:

1 . A method for fabricating a fin field-effect transistor (FinFET), comprising:
providing a substrate having a first region and a second region; forming a plurality of first fins on the substrate in the first region and a plurality of second fins on the substrate in the second region; forming a liner oxide layer on side surfaces of the first fins, side surfaces of the second fins and a surface of the substrate; forming an insulating barrier layer on a portion of the liner oxide layer in the first region; forming a precursor material layer on the insulating barrier layer in the first region and on the liner oxide layer in the second region; performing a curing annealing process to convert the precursor material layer into an insulation layer, a first oxide layer being formed on the side surfaces of the first fins, and a second oxide layer being formed on the side surfaces of the second fins; and removing a top portion of the insulation layer to form an isolation barrier layer and removing portions of the liner oxide layer, the insulating barrier layer, the first oxide layer and the second oxide layer higher than a surface of the isolation layer.

2 . The method according to claim 1 , wherein:
a feature size of the first fins is identical to a feature size of the second fins before forming the liner oxide layer; and a feature size of portions of the first fins higher than the surface of the isolation layer is greater than a feature size of portions of the second fins higher than the surface of the isolation layer after removing portions of the liner oxide layer, the insulation layer, the first oxide layer and the second oxide layer higher the surface of the isolation layer.

3 . The method according to claim 1 , wherein forming the insulating barrier layer comprises:
forming an insulating barrier film on the liner oxide layer; forming a patterned layer on the liner oxide layer in the first region; and removing a portion of the insulating barrier film in the second region by etching the insulating barrier film using the patterned layer as an etching mask.

4 . The method according to claim 1 , wherein:
a thickness difference between the first oxide layer and the second oxide layer is in a range of approximately 3 nm-5 nm; and a feature size difference between the portions of the first fins higher than the isolation layer and the portions of the second fins higher than the isolation layer is in a range of approximately 3 nm-5 nm.

5 . The method according to claim 1 , wherein:
the precursor material layer is flowable; and the precursor material layer is formed by a flowable chemical vapor deposition process.

6 . The method according to claim 5 , wherein:
precursors of the flowable chemical vapor deposition process include one or more of saline, disaline, methylsaline, dimethylsaline, trimethylsaline, tetramethylsaline, tetraethyl orthosilicate, (3-Aminopropyl) triethoxysilane, octamethyl cyclotetrasiloxane, 1,1,3,3-tetramethyldisiloxane, tetramethylcyclotetrasiloxane, trisilylamine, and disilylamine.

7 . The method according to claim 1 , wherein:
the curing annealing process is performed in a H 2 O-containing environment.

8 . The method according to claim 7 , wherein the H 2 O-containing environment further comprises:
one or more of O 2 and O 3 .

9 . The method according to claim 1 , wherein:
a temperature of the curing annealing process is in a range of approximately 400° C.-500° C.

10 . The method according to claim 1 , after the curing annealing process, further comprising:
performing a second annealing process to the precursor material layer, wherein:
a temperature of the second annealing process is in a range of approximately 900° C.-1100° C.; and
the second annealing process is performed in a N 2 environment.

11 . The method according to claim 1 , wherein:
the top portion of the insulation layer is removed by a wet etching process to form the isolation layer.

12 . The method according to claim 1 , wherein:
the liner oxide layer is formed by an in situ steam generation oxidation process.

13 . The method according to claim 1 , before forming the liner oxide layer, further comprising:
forming a hard mask layer on top surfaces of the first fins and top surfaces of the second fins, wherein:
the insulating barrier layer covers the hard mask layer in the first region; and
a top of the insulating barrier layer is higher than a top of the hard mask layer.

14 . The method according to claim 13 , before removing the top portion of the insulation layer, further comprising:
polishing the insulation layer until a top surface of the hard mask layer is exposed.

15 . The method according to claim 14 , further comprising:
removing the hard mask layer.

16 . A fin field-effect transistor (FinFET), comprising:
a substrate having a first region and a second region; a plurality of first fins formed on the substrate in the first region and a plurality of second fins with a feature side different from a feature size of the first fins formed on the substrate in the second region; a liner oxide layer formed on the surface of the substrate and bottom portions of side surfaces of the first fins and the second fins; an insulating barrier layer formed on the liner oxide layer in the first region; a first oxide layer formed between the bottom side surfaces of the first fins and the liner oxide layer in the first region and a second oxide layer with a thickness different from a thickness of the first oxide layer formed between the bottom side surfaces of the second fins and the liner oxide layer in the second region; and an isolation layer with a top surface lower than the top surfaces of the first fins and the second fins formed on the insulating barrier layer in the first region and on the liner oxide layer in the second region.

17 . The FinFET according to the claim 16 , wherein:
a feature size difference between the first fins and the second fins is in range of approximately 3 nm-5 nm; and a thickness difference between the first oxide layer and the second oxide layer is in a range of approximately 3 nm-5 nm.

18 . The FinFET according to claim 16 , wherein:
the insulating barrier layer is made of one of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and boron nitride.

19 . The FinFET according to claim 16 , wherein:
a thickness of the insulating barrier layer is in a range of approximately 30 Å-50 Å.

20 . The FinFET according to claim 19 , wherein:
the liner oxide layer is made of one of silicon oxide and silicon oxynitride.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Mao Gang

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H01L21/324

  Electricity · mapped topic