Method for producing a semiconductor chip and semiconductor chip

Patent metadata

Field	Value
Publication number	US-10396106-B2
Application number	US-201715594482-A
Country	US
Kind code	B2
Filing date	May 12, 2017
Priority date	May 13, 2016
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A method for producing a semiconductor chip ( 100 ) is provided, in which, during a growth process for growing a first semiconductor layer ( 1 ), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer ( 1 ), such that a lateral variation of a material composition of the first semiconductor layer ( 1 ) is produced. A semiconductor chip ( 100 ) is additionally provided.

First claim

The invention claimed is:

1. A method for producing a semiconductor chip, wherein, during a growth process for growing a first semiconductor layer, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer, such that a lateral variation of a material composition of the first semiconductor layer is produced, the lateral variation of the material composition comprising a gradient of a proportion of one or more constituents of the first semiconductor layer.

2. The method according to claim 1 , wherein the inhomogeneous lateral temperature distribution is selectively created, at least partly, by a locally varying light irradiation.

3. The method according to claim 2 , wherein the light irradiation comprises an irradiation with a laser.

4. The method according to claim 2 , wherein the light irradiation is varied locally by a light deflecting means and/or by a plurality of light sources that can be operated independently of one another, to create the inhomogeneous lateral temperature distribution.

5. The method according to claim 1 , wherein the inhomogeneous lateral temperature distribution is selectively created, at least partly, by a temperature distribution structure, which has at least one temperature distribution structure element, which effects a local increase or reduction of the temperature of the growing first semiconductor layer.

6. The method according to claim 5 , wherein the first semiconductor layer is grown on a growth substrate, and the temperature distribution structure is arranged on a side of the growth substrate that faces away from the first semiconductor layer.

7. The method according to claim 5 , wherein the first semiconductor layer is grown on a growth substrate, and the temperature distribution structure is arranged on a side of the growth substrate that faces toward the first semiconductor layer.

8. The method according to claim 5 , wherein the first semiconductor layer is grown on a growth substrate, and wherein the temperature distribution structure is arranged in direct contact with the growth substrate.

9. The method according to claim 5 , wherein the first semiconductor layer is grown on a growth substrate, and wherein, as viewed from the growth substrate, the temperature distribution structure is covered by a protective layer, and/or a protective layer is arranged between the temperature distribution structure and the growth substrate.

10. The method according to claim 5 , wherein the temperature distribution structure is embedded into a protective layer.

11. The method according to claim 5 , wherein the temperature distribution structure is embedded in a semiconductor layer and/or in a growth substrate.

12. The method according to claim 5 , wherein the temperature distribution structure remains in the finished semiconductor chip.

13. The method according to claim 5 , wherein the temperature distribution structure element has a material that absorbs electromagnetic radiation.

14. The method according to claim 5 , wherein the temperature distribution structure element has an elevation and/or a recess in a growth substrate.

15. The method according to claim 5 , wherein the temperature distribution structure element has a recess, in a growth substrate, arranged in which there is a thermal barrier material having a lesser thermal conductivity than the growth substrate.

16. The method according to claim 5 , wherein the temperature distribution structure element has an elevation, in a growth substrate, which effects a locally varying thermal coupling to a carrier, on which the growth substrate is arranged.

17. The method according to claim 1 , wherein the first semiconductor layer is at least a part of a waveguide layer and/or of an active layer.

18. The method according to claim 1 , wherein at least one second semiconductor layer is grown over the first semiconductor layer and a ridge waveguide is created in the second semiconductor layer.

19. The method according to claim 1 , wherein the first semiconductor layer is part of a semiconductor layer sequence having a plurality of semiconductor layers.

20. A semiconductor chip produced by means of a method according to claim 1 , having a first semiconductor layer that, along at least one direction of extent, has a lateral variation of a material composition resulting from a laterally varying temperature distribution during a growth process.

21. A method for producing a semiconductor chip, wherein, during a growth process for growing a first semiconductor layer, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer, such that a lateral variation of a material composition of the first semiconductor layer is produced,
wherein the inhomogeneous lateral temperature distribution is selectively created, at least partly, by a temperature distribution structure, which has at least one temperature distribution structure element, which effects a local increase or reduction of the temperature of the growing first semiconductor layer, and
wherein at least one of:
the first semiconductor layer is grown on a growth substrate, and the temperature distribution structure is arranged on a side of the growth substrate that faces away from the first semiconductor layer,
the temperature distribution structure is embedded into a protective layer,
the temperature distribution structure is embedded in a semiconductor layer and/or in a growth substrate,
the temperature distribution structure remains in the finished semiconductor chip, or
the temperature distribution structure element has a recess, in a growth substrate, arranged in which there is a thermal barrier material having a lesser thermal conductivity than the growth substrate.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Eichler Christoph
• Somers Andre
• Koenig Harald
• Stojetz Bernhard
• Loeffler Andreas
• Lell Alfred

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P74/238

  comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title