Multi-phase half bridge driver package and methods of manufacture

Patent metadata

Field	Value
Publication number	US-10396018-B2
Application number	US-201715822745-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Nov 27, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a plurality of half bridges each comprising a first power transistor die disposed over a second power transistor die;
a separate first metal lead attached to a bottom side of the first power transistor die and to a top side of the second power transistor die of each half bridge;
a separate or single second metal lead attached to a top side of the first power transistor die of each half bridge; and
a mold compound in which each half bridge and each metal lead are embedded,
wherein each first metal lead protrudes from a side face of the mold compound to form a half bridge output terminal,
wherein each second metal lead protrudes from a side face of the mold compound to form a first half bridge power terminal,
wherein at least part of a bottom side of the second power transistor die of each half bridge is not covered by the mold compound at a first main face of the mold compound to form a second half bridge power terminal,
wherein at least part of each second metal lead is not covered by the mold compound at a second main face of the mold compound opposite the first main face,
wherein each first metal lead has a notch which exposes one or more bond pads at the top side of the second power transistor die attached to that first metal lead.

2. The semiconductor package of claim 1 , wherein three half bridges are embedded in the mold compound, wherein two first metal leads protrude from a first side face of the mold compound, and wherein a single first metal lead protrudes from a second side face of the mold compound opposite the first side face.

3. The semiconductor package of claim 2 , wherein the separate or single second metal lead protrudes from a third side face of the mold compound in two locations and from a fourth side face of the mold compound opposite the third side face in a single location.

4. The semiconductor package of claim 1 , wherein the part of the bottom side of each second power transistor die not covered by the mold compound has bare semiconductor material exposed at the first main face of the mold compound.

5. The semiconductor package of claim 1 , wherein the plurality of half bridges forms a multi-phase brushless DC motor driver.

6. The semiconductor package of claim 1 , wherein the plurality of half bridges forms a multi-phase power converter driver.

7. The semiconductor package of claim 1 , further comprising a controller die embedded in the mold compound and configured to control the plurality of half bridges.

8. The semiconductor package of claim 7 , further comprising bond wire connections between the controller die and the one or more bond pads at the top side of each second power transistor die exposed by the notch in the corresponding first metal lead.

9. The semiconductor package of claim 1 , wherein the mold compound includes a ridge formed around a periphery of the second main face of the mold compound.

10. The semiconductor package of claim 9 , further comprising a thermally conductive and electrically insulative material disposed on the second main face of the mold compound and confined by the ridge.

11. A semiconductor package, comprising:
a plurality of half bridge assemblies each comprising a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side, each metal lead having a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead;
a controller die configured to control the first power transistor dies and the second power transistor dies;
a mold compound in which each power transistor die, each metal lead and the controller die are embedded; and
bond wire connections between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

12. The semiconductor package of claim 11 , wherein at least part of each second power transistor die is not covered by the mold compound at a first main face of the mold compound so that bare semiconductor material is exposed at the first main face of the mold compound.

13. A semiconductor package, comprising:
a plurality of half bridges each comprising a first power transistor die disposed over a second power transistor die;
a separate first metal lead attached to a bottom side of the first power transistor die and to a top side of the second power transistor die of each half bridge;
a separate or single second metal lead attached to a top side of the first power transistor die of each half bridge; and
a mold compound in which each half bridge and each metal lead are embedded,
wherein each first metal lead protrudes from a side face of the mold compound to form a half bridge output terminal,
wherein each second metal lead protrudes from a side face of the mold compound to form a first half bridge power terminal,
wherein at least part of a bottom side of the second power transistor die of each half bridge is not covered by the mold compound at a first main face of the mold compound to form a second half bridge power terminal,
wherein at least part of each second metal lead is not covered by the mold compound at a second main face of the mold compound opposite the first main face,
wherein the part of the bottom side of each second power transistor die not covered by the mold compound has bare semiconductor material exposed at the first main face of the mold compound.

Assignees

• Infineon Technologies Ag

Inventors

• Chiang Chau Fatt
• Cha Chan Lam
• Koo Wei Han
• Kucher Andreas
• Long Theng Chao

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/442

  of multiple leadframes in a single chip · CPC title

• H10W70/421

  Shapes or dispositions · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title