Method of forming an interference shield on a substrate

Patent metadata

Field	Value
Publication number	US-10375832-B2
Application number	US-201514956214-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Mar 27, 2014
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

First claim

What is claimed is:

1. A method of forming an interference shield on a substrate, the method comprising:
providing a die comprising contact points;
forming a build-up carrier adjacent a device side of the die, the build-up carrier comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die, wherein the die is embedded in the build-up carrier, wherein forming the build-up carrier comprises forming the plurality of alternating layers of conductive material and dielectric material on a sacrificial panel, and after forming the plurality of alternating layers of conductive material and dielectric material, separating the build-up carrier from the sacrificial panel; and
forming an interference shield on a top and sidewalls of the build-up carrier, wherein the portion of the interference shield on the top of the build-up carrier is non-planar.

2. The method of claim 1 , wherein the interference shield is formed on a surface of the build-up carrier adjacent a backside of the die.

3. The method of claim 2 , wherein forming the interference shield comprises sputtering a target material.

4. The method of claim 2 , wherein the interference shield comprises a plurality of layers of different conductive materials.

5. The method of claim 4 , wherein the plurality of different conductive materials comprise copper and nickel.

6. The method of claim 1 , wherein the sacrificial panel comprises a conductive material layer having a cavity therein and prior to forming the plurality of alternating layers of conductive material and dielectric material, the method comprises placing the die in the cavity and separating the build-up carrier from the sacrificial panel comprises removing the conductive material layer having the cavity.

7. The method of claim 1 , wherein at least one layer of the layers of patterned conductive material contacts the interference shield.

8. The method of claim 7 , wherein the at least one layer of the layers of patterned conductive material extends laterally to a width of the build-up carrier such that the at least one layer is exposed at least one side portion of opposing side portions of the build-up carrier and forming the interference shield comprises forming the interference shield on the at least one side portion.

9. The method of claim 7 , wherein the at least one layer of the layers of patterned conductive material defines a ground plane.

10. The method of claim 1 , wherein a layer of the layers of patterned conductive material is in direct electrical contact with the interference shield.

11. A method of forming an interference shield on a substrate, the method comprising:
providing a die comprising contact points;
forming a build-up carrier adjacent a device side of the die, the build-up carrier comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die, wherein forming the build-up carrier comprises forming the plurality of alternating layers of conductive material and dielectric material on a sacrificial panel and after forming the plurality of alternating layers of conductive material and dielectric material, separating the build-up carrier from the sacrificial panel; and
forming an interference shield on a portion of the build-up carrier, wherein the interference shield is formed on a surface of the build-up carrier adjacent a backside of the die, wherein forming the interference shield comprises sputtering a target material, and wherein the plurality of different conductive materials comprise copper and nickel.

12. The method of claim 11 , wherein the sacrificial panel comprises a conductive material layer having a cavity therein and prior to forming the plurality of alternating layers of conductive material and dielectric material, the method comprises placing the die in the cavity and separating the build-up carrier from the sacrificial panel comprises removing the conductive material layer having the cavity.

Assignees

• Intel Corp

Inventors

• Raorane Digvijay A
• Aygun Kemal
• Sobieski Daniel N
• Delaney Drew W

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title