Thin film based electromagnetic interference shielding with BBUL/coreless packages

Patent metadata

Field	Value
Publication number	US-9232686-B2
Application number	US-201414227929-A
Country	US
Kind code	B2
Filing date	Mar 27, 2014
Priority date	Mar 27, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

First claim

What is claimed is:

1. An apparatus comprising: a die comprising a first side and an opposite second side comprising a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and
an interference shield comprising a conductive material disposed on the first side of the die and a portion of the build-up carrier, wherein the at least one layer of the layers of patterned conductive material extends laterally to a width of the build-up carrier such that the at least one layer is exposed at least one side portion of opposing side portions of the build-up carrier and the interference shield contacts the at least layer at the at least one side portion.

2. The apparatus of claim 1 , wherein the interference shield comprises a thickness less than three microns.

3. The apparatus of claim 1 , wherein the interference shield comprises a plurality of layers of different conductive materials.

4. The apparatus of claim 3 , wherein the plurality of different conductive materials comprise copper and nickel.

5. The apparatus of claim 1 , wherein at least one layer of the layers of patterned conductive material contacts the interference shield.

6. The apparatus of claim 1 , wherein the at least one layer of the layers of patterned conductive material defines a ground plane.

7. An apparatus comprising: a computing device comprising a package including a microprocessor disposed in a build-up carrier, the microprocessor comprising a first side and an opposite second side comprising a device side with contact points, the build-up carrier coupled to the second side of the microprocessor, and comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; an interference shield comprising a conductive material disposed on the first side of the die and a portion of the build-up carrier; and a printed circuit board coupled to the package, wherein the at least one layer of the layers of patterned conductive material extends laterally to a width of the build-up carrier such that the at least one layer is exposed at least one side portion of opposing side portions of the build-up carrier and the interference shield contacts the at least layer at the at least one side portion.

8. The apparatus of claim 7 , wherein the interference shield comprises a thickness less than three microns.

9. The apparatus of claim 7 , wherein the interference shield comprises a plurality of layers of different conductive materials.

10. The apparatus of claim 9 , wherein the plurality of different conductive materials comprise copper and nickel.

11. The apparatus of claim 7 , wherein at least one layer of the layers of patterned conductive material contacts the interference shield.

12. The apparatus of claim 11 , wherein the at least one layer of the layers of patterned conductive material defines a ground plane.

Assignees

• Intel Corp

Inventors

• Raorane Digvijay A
• Aygun Kemal
• Sobieski Daniel N
• Delaney Drew W

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title