Integrated RF front end with stacked transistor switch

Patent metadata

Field	Value
Publication number	US-10374654-B2
Application number	US-201815917218-A
Country	US
Kind code	B2
Filing date	Mar 9, 2018
Priority date	Jun 23, 2004
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

First claim

What is claimed is:

1. A multiple-MOSFET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the circuit comprising:
a. a series transistor stack of J MOSFETs M N , N being an integer between 1 and J and J being an integer 2 or greater, each MOSFET M N having a source S N , a gate G N and a drain D N ,
b. an input signal node connected to the gate G 1 of a signal-input MOSFET M 1 of the MOSFET stack;
c. for 0<N<J, a series coupling between each drain D N and the source S (N+1) of a next higher MOSFET M (N+1) of the MOSFET transistor stack;
d. for 1<N≤J, a gate coupling element that is predominately capacitive connected directly between each gate G N and Vref, wherein, for 1<N≤J, each MOSFET M N is biased to avoid exceeding breakdown characteristics of the FET M N ; and where each gate G N is provided with a suitable bias voltage, and wherein the bias voltage is decoupled to Vref;
e. a source coupling for the FET stack between S 1 and Vref; and
f. a drain coupling for the FET stack between DJ and Vdrive;
wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M 2 to M N has associated and corresponding bias voltages VB 2 to VB N , wherein the bias voltages VB 2 to VB N may be individually selected to adjust the DC voltage divided across each corresponding and associated MOSFET M 2 to M N , and wherein the divided DC voltage across each MOSFET M 2 to M N may be controlled by the bias voltages VB 2 to VB N to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

2. The multiple-MOSFET stack circuit of claim 1 , wherein J is an integer 3 or greater.

3. The multiple-MOSFET stack circuit of claim 1 , wherein each MOSFET M 2 to M N has associated and corresponding bias resistors RB 2 to RB N connected to their associated and corresponding gates of G 2 to G N , wherein the bias resistors RB 2 to RB N are connected to associated and corresponding bias voltages VB 2 to VB N .

4. The multiple-MOSFET stack circuit of claim 1 , wherein each MOSFET M 2 to M N has a corresponding and associated gate capacitor CG 2 to CG N connected to the gate of each MOSFET M 2 to M N , and also connected to a ground reference, and wherein an RF voltage across each MOSFET M 2 to M N of the MOSFET transistor stack is determined by values of the associated and corresponding gate capacitors CG 2 to CG N .

5. The multiple-MOSFET stack circuit of claim 4 , wherein the DC and RF voltage across any one of the transistors M 2 to M N of the transistor stack is controlled by the associated and corresponding bias voltages and gate capacitors, respectively, and wherein the DC and RF voltages divided across any one of the individual MOSFETs M 2 to M N of the transistor stack are independently controlled.

6. The multiple-MOSFET stack circuit of claim 4 , wherein the DC voltages across the transistors M 2 to M N of the transistor stack are approximately equal.

7. The multiple-MOSFET stack circuit of claim 4 , wherein the RF voltages across the transistors M 2 to M N of the transistor stack are approximately equal.

8. The multiple-MOSFET stack circuit of claim 4 , wherein the DC voltages across the transistors M 2 to M N of the transistor stack are set to desired values.

9. The multiple-MOSFET stack circuit of claim 4 , wherein the RF voltages across the transistors M 2 to M N of the transistor stack are set to desired values.

10. The multiple-MOSFET stack circuit of claim 1 , further comprising an integrated RF Power Amplifier (PA) circuit, the integrated RF PA circuit comprising:
a. an input node that is the input signal node of claim 1 ; and
b. a matching, coupling and filtering circuit connected to the drive output node.

11. A Class A, B, C, AB, or F RF PA comprising a circuit according to claim 1 , wherein the multiple-MOSFET stack is configured as a primary amplifying device of the Class A, B, or C, AB, or F RF PA.

12. A quad mixer comprising a circuit according to claim 1 .

13. An RF power management circuit comprising a circuit according to claim 1 .

Assignees

• Psemi Corp

Inventors

• Burgener Mark L
• Cable James S

Classifications

• H01Q23/00

  Antennas with active circuits or circuit elements integrated within them or attached to them · CPC title

• H03G11/00

  Limiting amplitude; Limiting rate of change of amplitude · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title