Wiring substrate and semiconductor device

Patent metadata

Field	Value
Publication number	US-10366949-B2
Application number	US-201815866686-A
Country	US
Kind code	B2
Filing date	Jan 10, 2018
Priority date	Jul 16, 2014
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a first wiring structure; and
a second wiring structure stacked on the first wiring structure,
wherein the first wiring structure includes:
a first wiring layer;
a first insulating layer covering the first wiring layer, wherein the first insulating layer includes a first through hole that extends through the first insulating layer in a thickness-wise direction to expose an upper surface of the first wiring layer; and
a via wiring including an upper end surface exposed from an upper surface of the first insulating layer, wherein the first through hole of the first insulating layer is filled with the via wiring,

the second wiring structure includes:
a protective film formed on the upper surface of the first insulating layer;
a second wiring layer including a first wiring pattern, wherein the first wiring pattern is formed on the upper surface of the first insulating layer and the upper end surface of the via wiring; and
a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer,

the second wiring structure has a wiring density that is higher than a wiring density of the first wiring structure, and
the first wiring pattern of the second wiring layer comprises:
a first metal barrier film formed on the upper surface of the first insulating layer and the upper end surface of the via wiring;
a first metal film formed on the first metal barrier film; and
a first metal layer formed on the first metal film,
wherein the first metal layer includes an entirely roughened side surface and an entirely smooth side surface, and includes an upper surface comprising a partially roughened upper surface and a partially smooth upper surface,

the protective film is formed on the entirely smooth side surface of the first metal layer and the partially smooth upper surface of the first metal layer, and the partially roughened upper surface is partially attached to the second insulating layer,
each of the roughened side surface and the roughened upper surface of the first metal layer has a surface roughness that is smaller than a surface roughness of the first wiring layer, and
the first metal barrier film includes a peripheral portion that projects toward an outer side from the roughened side surface of the first metal layer.

2. The wiring substrate according to claim 1 , wherein:
the first metal film includes an entirely roughened side surface and an entirely smooth side surface;
the roughened side surface of the first metal film has a surface roughness that is smaller than the surface roughness of the first wiring layer; and
the peripheral portion of the first metal barrier film projects toward the outer side from the roughened side surface of the first metal layer and the roughened side surface of the first metal film.

3. The wiring substrate according to claim 2 , wherein the protective film is further formed along the smooth side surface of the first metal film and a side surface of the first metal barrier film.

4. The wiring substrate according to claim 1 , wherein:
the second wiring layer further includes a second wiring pattern, the second wiring pattern comprising:
a second metal barrier film formed on the upper surface of the first insulating layer;
a second metal film formed on the second metal barrier film and including a roughened side surface; and
a second metal layer formed on the second metal film and including a roughened side surface and a roughened upper surface,
wherein each of the roughened side surface of the second metal layer and the roughened side surface of the second metal film has a surface roughness that is smaller than the surface roughness of the first wiring layer, and
the second metal barrier film includes a peripheral portion that projects toward an outer side from the roughened side surface of the second metal layer and the roughened side surface of the second metal film.

5. The wiring substrate according to claim 4 , wherein the second wiring pattern is a solid pattern formed as a power supply plane or a ground plane.

6. The wiring substrate according to claim 1 , wherein:
the second wiring layer further includes a third wiring pattern, the third wiring pattern comprising:
a third metal barrier film formed on the upper surface of the first insulating layer;
a third metal film formed on the third metal barrier film and including a smooth side surface; and
a third metal layer formed on the third metal film and including a smooth side surface and a smooth upper surface.

7. The wiring substrate according to claim 6 , wherein the third metal barrier film includes a side surface that is flush with the smooth side surface of the third metal film and the smooth side surface of the third metal layer.

8. The wiring substrate according to claim 6 , wherein the third wiring pattern is finer than the first wiring pattern.

9. The wiring substrate according to claim 6 , wherein a second protective film is further formed along the smooth upper surface of the third metal layer, the smooth side surface of the third metal layer, the smooth side surface of the third metal film, and a side surface of the third metal barrier film to cover the third wiring pattern.

10. The wiring substrate according to claim 1 , wherein
the second wiring structure includes:
a third insulating layer stacked on the upper surface of the first insulating layer to cover the second wiring layer, wherein the third insulating layer includes a second through hole that exposes a part of the second wiring layer;
the second insulating layer stacked on the upper surface of the first insulating layer to cover the third insulating layer and the second wiring layer, wherein the second insulating layer includes a third through hole having a larger planar shape than the second through hole at a location overlapping the second through hole in a plan view; and
a third wiring layer including a via wiring to fill the second through hole and the third through hole, wherein the third wiring layer is electrically connected to the second wiring layer and stacked on the second insulating layer.

11. The wiring substrate according to claim 1 , wherein
the first insulating layer is a non-photosensitive insulative resin layer of which a main component is a thermosetting resin; and
the second insulating layer contains a photosensitive resin as a main component and is thinner than the first insulating layer.

12. A semiconductor device comprising:
a wiring substrate according to claim 1 ; and
a semiconductor chip mounted on the wiring substrate.

Assignees

• Shinko Electric Ind Co

Inventors

• Shimizu Noriyoshi
• Gozu Yusuke
• Furuichi Jun
• Rokugawa Akio
• Ito Takashi

Classifications

• H05K2203/0392

  Pretreatment of metal, e.g. before finish plating, etching · CPC title

• H05K2201/09845

  Stepped hole, via, edge, bump or conductor · CPC title

• H05K2201/0195

  Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K3/383

  by microetching · CPC title