Nanowire transistor structures with merged source/drain regions using auxiliary pillars

Patent metadata

Field	Value
Publication number	US-9257527-B2
Application number	US-201414181564-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 14, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.

First claim

What is claimed is:

1. A method comprising:
obtaining a first structure including a base substrate, a plurality of gate structures on the base substrate, and a plurality of semiconductor fin structures on the base substrate, each of the gate structures including a gate conductor and a vertically stacked arrangement of nanowires extending through the gate conductor, each fin structure including a plurality of semiconductor layers and being positioned between a pair of the gate structures, the step of obtaining the first structure including:
obtaining a starting substrate including alternating layers of first and second semiconductor materials, the first and second semiconductor materials being selectively etchable with respect to each other;
forming the semiconductor fin structures from the alternating layers of first and second semiconductor materials, the step of forming the semiconductor fin structures further including forming a plurality of parallel pads on the starting substrate and removing portions of the starting substrate between the pads;
forming the vertically stacked arrangement of the nanowires from the layers of second semiconductor material by forming a plurality of fins from the layers of first and second semiconductor materials within the starting substrate, the fins intersecting the fin structures, and selectively etching the layers of first semiconductor material from the fins, and
forming spacers on the fin structures and the gate structures, and
chopping the nanowires outside the gate structures and fin structures, and

epitaxially growing source/drain regions between the gate structures such that the source/drain regions contact the nanowires extending through the gate structures and one or more of the semiconductor layers of the fin structure.

2. The method of claim 1 , further including the step of forming the gate structures prior to epitaxially growing the source/drain regions.

3. The method of claim 1 , wherein the first semiconductor material includes silicon germanium and the gate structures are within ten nanometers or less of the fin structures.

4. The method of claim 3 , wherein the second semiconductor material is silicon and the nanowires comprise silicon.

5. The method of claim 1 , further including forming the spacers such that the nanowires include regions within the spacers adjoining the gate structures.

6. The method of claim 5 , further including the step of forming an electrical contact over the source/drain regions.

7. The method of claim 6 , wherein the second semiconductor layers are integral with the nanowires.

8. The method of claim 1 , wherein the nanowires comprise silicon.

9. The method of claim 8 , wherein the source/drain regions comprise doped silicon germanium.

10. The method of claim 8 , wherein the source/drain regions comprise carbon doped silicon.

Assignees

• IBM

Inventors

• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title