Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10355102-B2
Application number	US-201815941798-A
Country	US
Kind code	B2
Filing date	Mar 30, 2018
Priority date	Nov 15, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
anisotropically etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
forming a source/drain epitaxial layer in the source/drain space;
removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the first semiconductor layers from the exposed fin structure;
forming recesses toward the source/drain epitaxial layer;
forming inner spacers in the recesses; and
forming a gate dielectric layer covering the inner spacers and forming a gate electrode layer around the second semiconductor layer, wherein the gate electrode layer is isolated from the source/drain epitaxial layer by the inner spacer and the gate dielectric layer.

2. The method of claim 1 , wherein the recesses are formed in a region between the gate electrode layer and the source/drain epitaxial layer.

3. The method of claim 1 , wherein the removing the first semiconductor layers is carried out by selective wet etching.

4. The method of claim 3 , wherein facets of the recesses are selectively obtained by the selective etching the first semiconductor layers.

5. The method of claim 1 , wherein the inner spacer is formed by:
forming a dielectric layer in the recesses; and
anisotropically etching the dielectric layer.

6. The method of claim 5 , wherein the etched dielectric layer has a surface including a concave outer surface toward the source/drain region and a flat outer surface.

7. The method of claim 5 , wherein the inner spacers include at least one of silicon nitride and silicon oxide.

8. The method of claim 5 , wherein the inner spacers include at least one of SiOC, SiOCN and SiCN.

9. The method of claim 1 , wherein an interface of the gate dielectric layer and the inner spacer has shape including a concave shape and a flat shape.

10. The method of claim 1 , wherein in the removing the first semiconductor layers, the first semiconductor layers in the exposed fin structure are selectively etched, thereby leaving the second semiconductor layers remaining.

11. The method of claim 1 , wherein the second semiconductor layer is formed of nanowires having a thickness in a range from about 5 nm to about 15 nm and a width in a range from about 5 nm to about 15 nm.

12. The method of claim 1 , wherein the recesses are formed in remaining portions of the first semiconductor layers contacting the source/drain epitaxial layer in the removing the first semiconductor layers from the exposed fin structure.

13. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over a middle portion of the fin structure, wherein leaving a first end portion and a second end portion of the fin structure exposed;
removing the first semiconductor layers from the exposed first end portion and second end portion of the fin structure;
forming a source/drain epitaxial layer over the first end portion and the second end portion of the fin structure to form a source/drain region, wherein the epitaxial layer wraps around the second semiconductor layers of the first end portion and the second end portion;
removing the sacrificial gate structure, thereby exposing the middle portion of the fin structure;
removing the first semiconductor layers from the exposed middle portion of the fin structure;
forming recesses at both ends of locations of the first semiconductor layers toward the source/drain epitaxial layer;
forming dielectric spacers in the recesses; and
forming a gate dielectric layer covering the dielectric spacers and forming a gate electrode layer around the second semiconductor layers of the middle portion of the fin structure, wherein the gate electrode layer is isolated from the source/drain epitaxial layer by the dielectric spacers and the gate dielectric layer.

14. The method of claim 13 , wherein the dielectric spacers include at least one of silicon nitride and silicon oxide.

15. The method of claim 13 , wherein the second semiconductor layers are made of Si.

16. The method of claim 13 , wherein the second semiconductor layers are made of SiGe.

17. The method of claim 13 , wherein the dielectric spacers are in contact with the source/drain epitaxial layer.

18. The method of claim 17 , wherein the dielectric spacers in contact with the source/drain epitaxial layer having a facet including <100>, <110>, and <001>.

19. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over a middle portion of the fin structure, leaving a first end portion and a second end portion of the fin structure exposed;
removing the second semiconductor layers from the exposed first end portion and second end portion of the fin structure;
forming a source/drain epitaxial layer over the first end portion and the second end portion of the fin structure to form a source/drain region, wherein the epitaxial layer wraps around the first semiconductor layers of the first end portion and the second end portion;
removing the sacrificial gate structure, thereby exposing the middle portion of the fin structure;
removing the second semiconductor layers from the exposed middle portion of the fin structure;
forming recesses at both ends of locations of the second semiconductor layers toward the source/drain epitaxial layer;
forming inner spacers in the recesses; and
forming a gate dielectric layer covering the inner spacers and forming a gate electrode layer around the first semiconductor layers of the middle portion of the fin structure, wherein the gate electrode layer is isolated from the source/drain epitaxial layer by the inner spacers and the gate dielectric layer.

20. The method of claim 19 , wherein the inner spacers are formed in a region between the source/drain epitaxial layer and the gate electrode layer and have a shape including a concave shape and a flat shape.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chao-Ching
• Yang Yu-Lin
• Yun Wei-Sheng
• Hsu Chen-Feng
• Chen Tzu-Chiang

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66553 Primary

  Electricity · mapped topic