Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-10354934-B2
Application number	US-201815961839-A
Country	US
Kind code	B2
Filing date	Apr 24, 2018
Priority date	Jun 8, 2014
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die, wherein the semiconductor die comprises first and second opposing major surfaces and first and second sidewalls, wherein the first major surface of the semiconductor die is an active surface comprising openings to expose a plurality of die contact pads;
a plurality of external electrical contacts disposed on the die contact pads of the semiconductor die;
an encapsulant layer having a flowable polymeric material, wherein the encapsulant layer contacts and completely covers each of the first and second sidewalls of the semiconductor die, the encapsulant layer extending to contact and cover the first major surface of the semiconductor die without contacting the second major surface of the semiconductor die, wherein the entire second major surface of the semiconductor die is exposed; and
wherein the encapsulant layer comprises a convex surface profile extending across the first major surface of the semiconductor die.

2. The semiconductor package of claim 1 wherein the encapsulant layer comprises a non-planar surface profile extending across each of the first and second sidewalls of the semiconductor die.

3. The semiconductor package of claim 1 wherein each of the first and second sidewalls of the semiconductor die comprises first and second sidewall portions, wherein the second sidewall portion is laterally extended relative to the first sidewall portion to define a step profile of the first and second sidewalls.

4. The semiconductor package of claim 1 wherein a topmost planar surface of the encapsulant layer is coplanar to the second major surface of the semiconductor die.

5. The semiconductor package of claim 4 wherein external electrical contacts protrude from the convex surface profile of the encapsulant layer.

6. A semiconductor package comprising:
a semiconductor die, wherein the semiconductor die comprises first and second opposing major surfaces and first and second sidewalls, wherein the first major surface of the semiconductor die is an active surface comprising openings to expose a plurality of die contact pads;
a plurality of external electrical contacts disposed on the die contact pads of the semiconductor die;
a first encapsulant layer having top and bottom major surfaces, wherein the top major surface of the first encapsulant layer contacts and covers the first major surface of the semiconductor die, wherein the first encapsulant layer does not contact the second major surface of the semiconductor die and the entire second major surface of the semiconductor die is exposed; and
a second encapsulant layer distinct and separate from the first encapsulant layer, wherein the second encapsulant layer contacts and covers the bottom major surface of the first encapsulant layer and extends over the first and second sidewalls of the semiconductor die.

7. The semiconductor package of claim 6 wherein the external electrical contacts protrude outwardly from a bottom major surface of the second encapsulant layer.

8. The semiconductor package of claim 7 wherein the external electrical contacts comprise solder balls.

9. The semiconductor package of claim 6 wherein the first encapsulant layer contacts and covers the first and second sidewalls of the semiconductor die, wherein the first encapsulant layer separates the second encapsulant layer from the first and second sidewalls of the semiconductor die.

10. The semiconductor package of claim 9 wherein the first and second encapsulant layers comprise topmost surfaces that are coplanar to the second major surface of the semiconductor die.

11. The semiconductor package of claim 6 wherein the second encapsulant layer extends to contact and completely cover the first and second sidewalls of the semiconductor die, wherein a topmost surface of the second encapsulant layer is coplanar to the second major surface of the semiconductor die.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Dimaano Antonio Jr Bambalan
• Huang Rui
• Tan Hua Hong
• Le Kriangsak Sae
• Ho Beng Yeung
• De Vera Nelson Agbisit
• Robles Roel Adeva
• Micla Wedanni Linsangan

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W46/301

  for alignment · CPC title