Method of forming contacts for devices with multiple stress liners

Patent metadata

Field	Value
Publication number	US-9023696-B2
Application number	US-201113116672-A
Country	US
Kind code	B2
Filing date	May 26, 2011
Priority date	May 26, 2011
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.

First claim

What is claimed:

1. A method, comprising:
performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed and above a second region of said semiconducting substrate where a second type of transistor device will be formed;
forming a first stress inducing layer at least above said first etch stop layer formed above said first region, said first stress inducing layer adapted to induce a stress in a channel region of said first type of transistor device;
forming a first protection layer at least above said first stress inducing layer formed above said first region;
performing an etching process to remove said first etch stop layer from directly above said second region and to remove said first protection layer from directly above said first region;
after removing said first protection layer from directly above said first region, performing a second process operation to form a second etch stop layer at least above said second region; and
forming a second stress inducing layer at least above said second etch stop layer formed above said second region, said second stress inducing layer adapted to induce a stress in a channel region of said second type of transistor device.

2. The method of claim 1 , wherein said first process operation is a deposition process and said second process operation is a deposition process.

3. The method of claim 1 , wherein said first region is an NMOS region, said first type of transistor is an NMOS transistor, said second region is a PMOS region, and said second type of transistor is a PMOS transistor.

4. The method of claim 1 , wherein said first region is an PMOS region, said first type of transistor is a PMOS transistor, said second region is an NMOS region, and said second type of transistor is a NMOS transistor.

5. The method of claim 1 , wherein said first and second etch stop layers have the same approximate thickness.

6. The method of claim 1 , wherein, prior to removing said first etch stop layer from above said second region, performing a second etching process to remove a layer of material that was previously formed above said second region of said semiconducting substrate.

7. The method of claim 1 , wherein said first etch stop layer is formed on a surface of said semiconducting substrate in said first region, and wherein said second etch stop layer is formed on a surface of said semiconducting substrate in said second region.

8. The method of claim 1 , wherein said first and second etch stop layers are comprised of silicon dioxide and said first and second stress inducing layers are comprised of silicon nitride.

9. The method of claim 3 , wherein said first stress inducing layer is adapted to induce a tensile stress in said channel region of said NMOS transistor, and wherein said second stress inducing layer is adapted induce a compressive stress in said channel region of said PMOS transistor.

10. The method of claim 3 , wherein said first stress inducing layer is adapted to induce a compressive stress in said channel region of said PMOS transistor, and wherein said second stress inducing layer is adapted induce a tensile stress in said channel region of said NMOS transistor.

11. A method, comprising:
performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed and above a second region of said semiconducting substrate where a second type of a transistor will be formed;
forming a first stress inducing layer above said first etch stop layer formed above said first and second regions, said first stress inducing layer adapted to induce a stress in a channel region of said first type of transistor device;
forming a first protection layer above said first stress inducing layer formed above said first and second regions;
performing at least one first etching process to remove said first protection layer and said first stress inducing layer from above said second region;
performing at least one second etching process to remove said first etch stop layer formed directly above said second region and to remove said first protection layer from above said first stress inducing layer formed directly above said first region;
after removing said first etch stop layer from directly above said second region, performing a second process operation to form a second etch stop layer at least above said second region of said semiconducting substrate; and
forming a second stress inducing layer at least above said second etch stop layer formed above said second region, said second stress inducing layer adapted to induce a stress in a channel region of said second type of transistor device.

12. The method of claim 11 , wherein said first and second etch stop layers have the same approximate thickness.

13. The method of claim 11 , wherein said first etch stop layer is formed on a surface of said semiconducting substrate in said first and second regions, and wherein said second etch stop layer is formed on a surface of said semiconducting substrate in said second region.

14. The method of claim 11 , further comprising forming a second protection layer at least above said second stress inducing layer formed above said second region.

15. The method of claim 14 , wherein said first and second etch stop layers and said first and second protection layers comprise silicon dioxide and said first and second stress inducing layers comprise silicon nitride.

16. The method of claim 11 , wherein forming said second etch stop layer at least above said second region comprises forming a portion of said second etch stop layer above said first region, and wherein forming said second stress inducing layer at least above said second etch stop layer formed above said second region comprises forming a portion of said second stress inducing layer above said portion of said second etch stop layer formed above said first region.

17. The method of claim 16 , further comprising forming a second protection layer above said second stress inducing layer formed above said first and second regions.

18. The method of claim 1 , wherein forming said first stress inducing layer and said first protection layer at least above said first region comprises forming a portion of said first stress inducing layer and a portion of said first protection layer above said second region, forming a patterned mask layer to cover said first region and expose said second region, and performing one or more etch processes to remove said portions of said first stress inducing layer and said first etch stop layer from above said second region.

19. The method of claim 1 , further comprising forming a second protection layer at least above said second stress inducing layer formed above said second region.

20. The method of claim 19 , wherein forming said second etch stop layer, said second stress inducing layer, and said second protection layer at least above said second region comprises forming a portion of said second etch stop layer, a portion of said second stress inducing layer, and a portion of said second protection layer above said first stress inducing layer formed above said first region, forming a patterned mask layer to cover said second region and expose said first region, and performing one or more etch processes to remove said portions of said second protection layer, said second stress inducing layer, and said second etch stop lay

Assignees

• Baars Peter
• Lepper Marco
• Scheiper Thilo
• Globalfoundries Inc

Inventors

• Baars Peter
• Lepper Marco
• Scheiper Thilo

Classifications

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0167 Primary

  Manufacturing their channels · CPC title

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title