Callback based constraint processing for clock domain independence

Patent metadata

Field	Value
Publication number	US-9977850-B2
Application number	US-201615207898-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Jul 12, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

First claim

What is claimed is:

1. A method of performing timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence, the method comprising:
generating a timing graph representation of the integrated circuit design, wherein the timing graph includes nodes interconnected by edges;
loading timing abstracts representing the nodes of the timing graph;
obtaining, using a processor, a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks, wherein each timing tag indicates a clock domain;
applying a design change;
determining, using the processor, one or more modified timing tags that are added or changed as a result of the design change;
processing the timing constraints associated with the modified timing tags as callbacks;
re-computing the timing result; and
manufacturing a physical implementation of the integrated circuit based on the timing analysis.

2. The method according to claim 1 , wherein the applying the design change includes adding or deleting one or more of the edges.

3. The method according to claim 1 , wherein the determining the one or more modified timing tags includes maintaining an incremental timing tag invalidation list based on the applying the design change, the incremental timing tag invalidation list including a list of modified edges that are added or deleted as a result of the applying the design change.

4. The method according to claim 3 , wherein the determining the one or more modified timing tags includes examining the timing tag associated with a sink node of one of the modified edges in the incremental timing tag invalidation list.

5. The method according to claim 4 , wherein the determining the one or more modified timing tag includes identifying the sink node of the one of the modified edges as being added based on the design change or determining that the timing tag associated with the sink node of the one of the modified edges is changed based on the design change.

6. The method according to claim 5 , wherein the determining the one or more modified timing tags includes adding the timing tags of the nodes that fan out from the sink node of the one of the modified edges to the incremental timing tag invalidation list.

7. A system to perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence, the system comprising:
a memory device configured to store a timing graph representation of the integrated circuit design, wherein the timing graph includes nodes interconnected by edges; and
a processor configured to load timing abstracts representing the nodes of the timing graph, obtain a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks, wherein each timing tag indicates a clock domain, apply a design change, determine one or more modified timing tags that are added or changed as a result of the design change, process the timing constraints associated with the modified timing tags as callbacks, and re-compute the timing result, wherein a physical implementation of the integrated circuit design based on the timing analysis is manufactured.

8. The system according to claim 7 , wherein the processor adds or deletes one or more of the edges to apply the design change.

9. The system according to claim 7 , wherein the processor determines the one or more modified timing tags based on maintaining an incremental timing tag invalidation list based on the applying the design change, the incremental timing tag invalidation list including a list of modified edges that are added or deleted as a result of the applying the design change.

10. The system according to claim 9 , wherein the processor determines the one or more modified timing tags based on examining the timing tag associated with a sink node of one of the modified edges in the incremental timing tag invalidation list.

11. The system according to claim 10 , wherein the processor determines the one or more modified timing tags based on identifying the sink node of the one of the modified edges as being added based on the design change or determining that the timing tag associated with the sink node of the one of the modified edges is changed based on the design change.

12. The system according to claim 11 , wherein the processor determines the one or more modified timing tags based on adding the timing tags of the nodes that fan out from the sink node of the one of the modified edges to the incremental timing tag invalidation list.

13. The system according to claim 12 , wherein the processor determines, incrementally, whether the timing tags of the nodes that fan out from the sink node of the one of the modified edges are among the one or more modified timing tags.

14. A computer program product for performing timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
generating a timing graph representation of the integrated circuit design, wherein the timing graph includes nodes interconnected by edges;
loading timing abstracts representing the nodes of the timing graph;
obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks, wherein each timing tag indicates a clock domain;
applying a design change;
determining one or more modified timing tags that are added or changed as a result of the design change;
processing the timing constraints associated with the modified timing tags as callbacks; and
re-computing the timing result, wherein a physical implementation of the integrated circuit based on the timing analysis is manufactured.

15. The computer program product according to claim 14 , wherein the applying the design change includes adding or deleting one or more of the edges.

16. The computer program product according to claim 14 , wherein the determining the one or more modified timing tags includes maintaining an incremental timing tag invalidation list based on the applying the design change, the incremental timing tag invalidation list including a list of modified edges that are added or deleted as a result of the applying the design change.

17. The computer program product according to claim 16 , wherein the determining the one or more modified timing tags includes examining the timing tag associated with a sink node of one of the modified edges in the incremental timing tag invalidation list.

18. The computer program product according to claim 17 , wherein the determining the one or more modified timing tag includes identifying the sink node of the one of the modified edges as being added based on the design change or determining that the timing tag associated with the sink node of the one of the modified edges is changed based on the design change.

19. The computer program product according to claim 18 , wherein the determining the one or more modified timing tags includes adding the timing tags o

Assignees

• IBM

Inventors

• Abdul Naiju K
• Bhanji Adil
• Gupta Hemlata
• Kalafala Kerim
• Rubin Alex
• Verma Manish

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F17/5081

  Physics · mapped topic