Bond rings in semiconductor devices and methods of forming same

Patent metadata

Field	Value
Publication number	US-10351418-B2
Application number	US-201815952700-A
Country	US
Kind code	B2
Filing date	Apr 13, 2018
Priority date	Mar 24, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

First claim

What is claimed is:

1. A method comprising:
forming a first plurality of bond pads on a device substrate, topmost surfaces of the first plurality of bond pads being above a topmost surface of the device substrate;
depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads; and
etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads, topmost surfaces of the spacers being below the topmost surfaces of the first plurality of bond pads and above the topmost surface of the device substrate.

2. The method of claim 1 , wherein a distance between the topmost surfaces of the spacers and the topmost surfaces of the first plurality of bond pads is between about 100 Å and about 200 Å.

3. The method of claim 1 , wherein forming the first plurality of bond pads on the device substrate comprises patterning the device substrate to form a plurality of recesses, portions of the device substrate interposed between adjacent recesses forming a plurality of contact areas.

4. The method of claim 3 , wherein forming the first plurality of bond pads on the device substrate further comprises:
depositing a first conductive material over the plurality of contact areas; and
depositing a second conductive material over the first conductive material, the second conductive material being different from the first conductive material.

5. The method of claim 3 , wherein the plurality of contact areas have a height between about 0.5 μm and about 2 μm.

6. The method of claim 1 , further comprising:
forming a second plurality of bond pads on a cap substrate; and
bonding the cap substrate to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

7. The method of claim 1 , wherein the first plurality of bond pads have a width between about 50 μm and about 60 μm.

8. A method comprising:
bonding a device substrate to a carrier substrate;
patterning a surface of the device substrate opposing the carrier substrate to form a contact area;
forming a first bond ring on the contact area;
depositing a spacer layer over a topmost surface and along sidewalls of the first bond ring; and
patterning the spacer layer to form spacers on sidewalls of the first bond ring, topmost surfaces of the spacers being below a topmost surface of the first bond ring and above a topmost surface of the device substrate.

9. The method of claim 8 , wherein forming the first bond ring on the contact area comprises:
forming a first conductive material over the contact area; and
forming a second conductive material over the first conductive material, the second conductive material being different from the first conductive material.

10. The method of claim 8 , further comprising:
forming a second bond ring on a cap substrate; and
eutectically bonding the second bond ring to the first bond ring.

11. The method of claim 10 , wherein a width of the second bond ring is greater than a width of the first bond ring.

12. The method of claim 8 , depositing the spacer layer over the topmost surface and along the sidewalls of the first bond ring further comprises depositing the spacer layer along sidewalls of the contact area.

13. The method of claim 8 , further comprising patterning the device substrate to form a micro-electromechanical systems (MEMS) structure.

14. The method of claim 8 , wherein bonding the device substrate to the carrier substrate comprises a fusion bonding process.

15. A package comprising:
a device substrate comprising a micro-electromechanical systems (MEMS) structure, wherein the device substrate comprises a contact area;
a first bond ring on the contact area, each of sidewalls of the first bond ring being aligned with a respective one of sidewalls of the contact area; and
spacers on the sidewalls of the first bond ring and on the sidewalls of the contact area, topmost surfaces of the spacers being below a topmost surface of the first bond ring.

16. The package of claim 15 , further comprising a cap substrate bonded to the device substrate, wherein the cap substrate comprises a second bond ring, and wherein the second bond ring is in physical contact with the first bond ring.

17. The package of claim 16 , wherein a width of the second bond ring is greater than a width of the first bond ring.

18. The package of claim 16 , further comprising a carrier substrate bonded to the device substrate, the device substrate being interposed between the carrier substrate and the cap substrate.

19. The package of claim 15 , wherein a distance between the topmost surfaces of the spacers and the topmost surface of the first bond ring is between about 100 Å and about 200 Å.

20. The package of claim 15 , wherein the first bond ring comprises:
a first conductive layer comprising a first conductive material; and
a second conductive layer over the first conductive layer, the second conductive layer comprising a second conductive material different from the first conductive material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Ming
• Liu Ping-Yin
• Yu Chung-Yi
• Tu Yeur-Luen

Classifications

• H10W72/981

  Auxiliary members, e.g. spacers · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/019

  of bond pads · CPC title