Method of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-9496179-B2
Application number	US-201514833922-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	Aug 25, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising: forming a plurality of active patterns extending along a first direction and spaced apart from each other along a second direction across the first direction, on a substrate; forming a gate electrode across extending along the second direction to cross the plurality of the active patterns; forming a first contact disposed at one side of the gate electrode and extending along the second direction to be electrically connected to the plurality of the active patterns; forming a second contact connected to the gate electrode; and forming a third contact disposed at the side of the gate electrode and extending along the second direction from an end of the first contact, wherein the forming of the first contact comprises performing an exposure process using one photomask, the forming of the third contact comprises performing an exposure process using a photomask different from said one photomask, and wherein the third contact is formed such that a bottom surface of the third contact is disposed at a level in the device that is lower than that at which a top surface of the first contact is disposed.

2. The manufacturing method of claim 1 , wherein the first and third contacts are formed such that a top surface of the third contact and the top surface of the first contact are located at the same level in the device.

3. The manufacturing method of claim 1 , further comprising forming on the substrate a common conductive line electrically connected to the third contact, whereby the common conductive line can apply a voltage to the plurality of the plurality of the active patterns through the third contact and the first contact.

4. The manufacturing method of claim 3 , further comprising forming a via on and electrically connected to the third contact, and
wherein the common conductive line is formed on the via as electrically thereto such that the via is interposed between the common conductive line and the third contact, and the third contact is electrically connected to the common conductive line through the via.

5. The manufacturing method of claim 1 , wherein the first, second and third contacts are formed such that top surfaces thereof are located at the same level in the device.

6. The manufacturing method of claim 1 , wherein the third contact is formed using the same photomask as that used to form the second contact.

7. The manufacturing method of claim 6 , wherein the forming of the first, second and third contacts comprise: forming an interlayer insulating layer covering the plurality of the active patterns and the gate electrode on the substrate; performing a photolithography process using a first photomask to form a first contact hole through the interlayer insulating layer at the side of the gate electrode; and performing a photolithography process using a second photomask to concurrently form a second contact hole through the interlayer insulating layer to expose the gate electrode, and a third contact hole through the interlayer insulating layer at the side of the gate electrode, wherein the second contact hole is spaced apart from the first contact hole and the third contact hole extends from the first contact hole along the second direction, and the first through third contacts are formed in the first through third contact holes, respectively.

8. The manufacturing method of claim 7 , wherein the forming of the first, second and third contacts comprise:
forming, on the interlayer insulating layer, a conductive layer filling the first, second and third contact holes; and
planarizing the conductive layer until a top surface of the interlayer insulating layer is exposed.

9. The manufacturing method of claim 1 , wherein the second contact is formed using a photomask different from the photomask used to form the third contact.

10. The manufacturing method of claim 9 , wherein the forming the first, second and third contacts comprise: forming an interlayer insulating layer covering the plurality of the active patterns and the gate electrode on the substrate; performing a photolithography process using a first photomask to form a first contact hole through the interlayer insulating layer at the side of the gate electrode; performing a photolithography process using a second photomask to form a second contact hole through the interlayer insulating layer to expose the gate electrode; and performing a photolithography process using a third photomask to form a third contact hole through the interlayer insulating layer at the side of the gate electrode, wherein the second contact hole is spaced apart from the first contact hole and the third contact hole extends from the first contact hole along the second direction, and the first, second and third contacts are formed in the first, second and third contact holes, respectively.

11. The manufacturing method of claim 10 , wherein the forming of the first, second and third contacts comprise:
forming, on the interlayer insulating layer, a conductive layer filling the first through, second and contact holes; and
planarizing the conductive layer until a top surface of the interlayer insulating layer is exposed.

12. The manufacturing method of claim 9 , wherein the forming of the first, second and third contacts comprise: forming a first interlayer insulating layer covering the plurality of the active patterns and the gate electrode on the substrate; performing a photolithography process using a first photomask to form a first contact hole through the first interlayer insulating layer at the side of the gate electrode; performing a photolithography process using a second photomask to form a second contact hole through the first interlayer insulating layer to expose the gate electrode; forming the first contact and the second contact in the first contact hole and the second contact hole, respectively; forming, on the first interlayer insulating layer, a second interlayer insulating layer covering the first contact and the second contact; performing a photolithography process using a third photomask to form a third contact hole through at least a portion of the first interlayer insulating layer and the second interlayer insulating layer; and forming the third contact in the third contact hole, wherein the third contact hole exposes at least a portion of the first contact.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Baek Sanghoon
• Park Sunyoung
• Oh Sang-Kyu
• Kim Jintae
• Won Hyosig

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title