Frequency detection circuit and reception circuit

Patent metadata

Field	Value
Publication number	US-9520883-B2
Application number	US-201514834927-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Oct 2, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector.

First claim

What is claimed is:

1. A frequency detection circuit comprising:
a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value corresponding to a center value of an amplitude level of input data, and the input data at first timing of a first clock;
a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value, and the input data at the first timing;
a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock having a phase shifted from that of the first clock;
a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas based on the first comparison result, the second comparison result, and the third comparison result; and
a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector so as to determine whether a second frequency of the first clock or the second clock is higher or lower with respect to a first frequency of the input data.

2. The frequency detection circuit according to claim 1 ,
wherein among the three areas, a first area is set to have a width based on a slew rate of the input data, the second threshold value, and the third threshold value between a second area and a third area.

3. The frequency detection circuit according to claim 1 ,
wherein the phase rotation detector is configured to output a signal for changing the second frequency based on the rotation direction when a change of the edge spreading over the three areas in the same rotation direction is detected from the detection result by the phase detector.

4. The frequency detection circuit according to claim 1 ,
wherein the phase rotation detector is configured to detect the rotation direction each time the phase detector receives the detection result, and continue to output a signal for changing the second frequency based on the rotation direction until the rotation direction is changed even if the detection result is not changed.

5. A reception circuit comprising:
a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value corresponding to a center value of an amplitude level of input data, and the input data at first timing of a first clock;
a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value, and the input data at the first timing;
a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock having a phase shifted from that of the first clock;
a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas based on the first comparison result, the second comparison result, and the third comparison result;
a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector so as to determine whether a second frequency of the first clock or the second clock is higher or lower with respect to a first frequency of the input data;
a fourth comparison circuit configured to output a fourth comparison result produced by comparison between the input data and the first threshold value at the first timing;
a phase control unit configured to detect a phase difference between the input data, and the first clock or the second clock based on the third comparison result and the fourth comparison result; and
a clock generation unit configured to generate the first clock and the second clock based on the phase difference and the rotation direction.

6. A reception circuit comprising:
a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value corresponding to a center value of an amplitude level of input data, and the input data at first timing of a first clock;
a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value, and the input data at the first timing;
a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock having a phase shifted from that of the first clock;
a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas based on the first comparison result, the second comparison result, and the third comparison result;
a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector so as to determine whether a second frequency of the first clock or the second clock is higher or lower with respect to a first frequency of the input data;
a selection unit configured to select either the first comparison result or the second comparison result as a first data determination result based on a second data determination result before the one-bit width time;
a phase control unit configured to detect a phase difference between the input data, and the first clock or the second clock based on the third comparison result and the first data determination result; and
a clock generation unit configured to generate the first clock and the second clock based on the phase difference and the rotation direction.

Assignees

• Fujitsu Ltd

Inventors

• Shibasaki Takayuki

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title