Techniques for adjusting clock signals to compensate for noise

Patent metadata

Field	Value
Publication number	US-9565036-B2
Application number	US-201013378024-A
Country	US
Kind code	B2
Filing date	May 31, 2010
Priority date	Jun 30, 2009
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.

First claim

What is claimed is:

1. A system comprising:
a first integrated circuit chip comprising
a first internal clock buffer circuit, which draws current that is sourced from a first supply voltage, the first internal clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) based on the first supply voltage, and
a first interface circuit to output data synchronously with respect to the first internal clock signal;

a second integrated circuit chip comprising
a supply voltage node that receives the first supply voltage from the first integrated circuit chip,
a second internal clock buffer circuit, which draws current from the supply voltage node that is sourced from the first supply voltage, the second internal clock buffer circuit to generate a second internal clock signal that exhibits second PSIJ based on the first supply voltage, and
a second interface circuit to receive the data synchronously with respect to the second internal clock signal; and

wherein the second PSIJ compensates for timing error that is based on the first PSIJ.

2. The system of claim 1 , wherein at least one of the first and the second integrated circuit chips further comprises a regulator circuit that generates a second supply voltage using the first supply voltage such that one of the respective first and second internal clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

3. The system of claim 1 wherein at least one of the first and the second integrated circuit chips draws current from a second supply voltage that is derived from the first supply voltage.

4. The system of claim 1 wherein the first integrated circuit chip further includes a clock receiver circuit, wherein the first internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the second integrated circuit chip.

5. The system of claim 1 wherein the second integrated circuit chip further includes a clock receiver circuit, wherein the second internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the first integrated circuit chip.

6. The system of claim 1 wherein one of the first and the second integrated circuit chips is a memory device and the other of the first and the second integrated circuit chips is a controller device.

7. A first integrated circuit chip comprising:
a first clock buffer circuit, which draws current that is sourced from a first supply voltage, the first clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) that is based on the first supply voltage;
an interface circuit to output data to a second integrated circuit chip, synchronously with respect to the first internal clock signal, wherein the second integrated circuit chip receives the data synchronously with respect to a second internal clock signal and receives the first supply voltage provided by the first integrated circuit, wherein the second internal clock signal exhibits second PSIJ that is based on the first supply voltage and is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage; and
wherein the second PSIJ compensates for timing error that is based on the first PSIJ.

8. The first integrated circuit chip of claim 7 , wherein a delay characteristic of the first clock buffer circuit varies with respect to noise present in the first supply voltage.

9. The first integrated circuit chip of claim 7 , wherein the first clock buffer circuit is part of an on chip clock distribution network.

10. The first integrated circuit chip of claim 7 , wherein at least one of the first and the second integrated circuit chips further comprises a regulator circuit that generates a second supply voltage using the first supply voltage such that one of the respective first and second clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

11. The first integrated circuit chip of claim 7 , wherein the interface circuit draws current from a second supply voltage that is derived from the first supply voltage.

12. The first integrated circuit chip of claim 7 , wherein the first integrated circuit chip further includes a clock receiver circuit, wherein the first internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the second integrated circuit chip.

13. The first integrated circuit chip of claim 7 , wherein the second integrated circuit chip further includes a clock receiver circuit, wherein the second internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the first integrated circuit chip.

14. The first integrated circuit chip of claim 7 , wherein one of the first and the second integrated circuit chips is a memory device and the other of the first and the second integrated circuit chips is a controller device.

15. A first integrated circuit chip comprising:
a first clock buffer circuit, which draws current that is sourced from a first supply voltage, the first clock buffer circuit to provide a first internal clock signal that exhibits first power supply induced jitter (PSIJ) based on the first supply voltage;
a supply voltage terminal to provide the first supply voltage to a second integrated circuit chip;
an interface circuit to receive data from the second integrated circuit chip, synchronously with respect to the first internal clock signal, wherein the second integrated circuit chip transmits the data to the first integrated circuit chip synchronously with respect to a second internal clock signal that exhibits second power supply induced jitter (PSIJ), wherein the second internal clock signal is generated by a second clock buffer circuit, which draws current that is sourced from the first supply voltage, wherein the second PSIJ is based on the first supply voltage; and
wherein the second PSIJ compensates for timing error that is based on the first PSIJ.

16. The first integrated circuit chip of claim 15 , wherein at least one of the first and the second integrated circuit chips further comprises a regulator circuit that generates a second supply voltage using the first supply voltage such that one of the respective first and second clock buffer circuits draws current that is sourced from the first supply voltage via the second supply voltage.

17. The first integrated circuit chip of claim 15 , wherein the interface circuit draws current from a second supply voltage that is derived from the first supply voltage.

18. The first integrated circuit chip of claim 15 , wherein the first integrated circuit chip further includes a clock receiver circuit, wherein the first internal clock signal is derived from an external timing signal that is received at the clock receiver circuit, and wherein the external timing signal is provided by the second integrated circuit chip.

19. The first integrated circuit chip of claim 15 , wherein the second integrated circuit chip further includes a clock receiver circuit, wherein the second internal clock signal is derived from an external timing signal that is received at the clock receiver

Assignees

• Zerbe Jared
• Batra Pradeep
• Leibowitz Brian
• Rambus Inc

Inventors

• Zerbe Jared
• Batra Pradeep
• Leibowitz Brian

Classifications

• H03K5/1252

  Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H04L25/0264 Primary

  Arrangements for coupling to transmission lines (duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878) · CPC title