Transceiver including a high latency communication channel and a low latency communication channel

Patent metadata

Field	Value
Publication number	US-9306621-B2
Application number	US-201414498383-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Nov 7, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

First claim

What is claimed is:

1. A transceiver, comprising:
a high latency communication channel; and
a low latency communication channel that is a bypass channel for the high latency communication channel, the high latency communication channel configured to:
convert a serial input signal to first parallel signals, and

the low latency communication channel configured to:
convert the first parallel signals to second parallel signals, wherein a number of signals in the second parallel signals is more than a number of signals in the first parallel signals; and
output a delayed version of the second parallel signals;

wherein one of the first parallel signals from the high latency communication channel or the delayed version of the second parallel signals from the low latency communication channel is selected for conversion to a serial output signal.

2. The transceiver of claim 1 , further comprising:
a digital core included in the low latency communication channel;
a first phase interpolator configured to receive a first clock signal and a first control signal from the digital core, and generate a receiver clock signal that is a first version of the first clock signal that is phase adjusted according to the first control signal; and
a second phase interpolator configured to receive the first clock signal and a second control signal from the digital core, and generate a transmitter clock signal that is a second version of the first clock signal that is phase adjusted at least according to the second control signal.

3. The transceiver of claim 2 , further comprising a delay-locked loop (DLL) configured to phase align the transmitter clock signal with the receiver clock signal.

4. The transceiver of claim 1 , wherein the delayed version of the second parallel signals is provided by a first-in first-out (FIFO) included in the low latency communication channel.

5. The transceiver of claim 4 , wherein the FIFO includes:
depth adjuster logic configured to receive a FIFO depth selection signal;
wherein the depth adjustor circuit is configured to modify a depth of the FIFO according to the received FIFO depth selection signal.

6. The transceiver of claim 1 , wherein the high latency communication channel is further configured to:
convert the first parallel signals to third parallel signals; and
output a delayed version of the third parallel signals;
wherein one of the delayed version of the third parallel signals from the high latency communication channel or the delayed version of the second parallel signals from the low latency communication channel is selected for conversion to a serial output signal.

7. The transceiver of claim 6 , wherein the delayed version of the third parallel signals is provided by a FIFO included in the high latency communication channel.

8. The transceiver of claim 6 , wherein the number of signals in the second parallel signals is less than the number of signals in the third parallel signals.

9. The transceiver of claim 6 , wherein the third parallel signals are digital signals.

10. A method, comprising:
converting a serial input signal to first parallel signals in a high latency communication channel of a transceiver;
converting the first parallel signals to second parallel signals in a low latency communication channel of the transceiver, a number of signals in the second parallel signals being more than a number of signals in the first parallel signals, the low latency communication channel being a bypass channel for the high latency communication channel;
outputting a delayed version of the second parallel signals from the low latency communication channel; and
selecting one of the first parallel signals from the high latency communication channel or the delayed version of the second parallel signals from the low latency communication channel for conversion to a serial output signal.

11. The method of claim 10 , wherein the delayed version of the second parallel signals is provided by a first-in first-out (FIFO) included in the low latency communication channel.

12. The method of claim 11 , wherein a depth of the FIFO is modifiable.

13. The method of claim 10 , further comprising:
phase adjusting a first clock signal to generate a receiver clock signal according to a first control signal; and
phase adjusting the first clock signal to generate a transmitter clock signal according to at least a second control signal.

14. The method of claim 13 , further comprising phase aligning the transmitter clock signal with the receiver clock signal.

15. The method of claim 13 , further comprising:
detecting a phase difference between the transmitter clock signal and the receiver clock signal;
transmitting a phase difference signal in response to detecting a phase difference between the transmitter clock signal and the receiver clock signal; and
generating the second control signal using at least the phase difference signal.

16. The method of claim 10 , further comprising:
converting the first parallel signals to third parallel signals in the high latency communication channel;
outputting a delayed version of the third parallel signals from the high latency communication channel; and
selecting one of the delayed version of the third parallel signals from the high latency communication channel or the delayed version of the second parallel signals from the low latency communication channel for conversion to a serial output signal.

17. The method of claim 16 , wherein the delayed version of the third parallel signals is provided by a FIFO included in the high latency communication channel.

18. The method of claim 16 , wherein the number of signals in the second parallel signals is less than the number of signals in the third parallel signals.

19. The method of claim 16 , wherein the third parallel signals are digital signals.

Assignees

• Broadcom Corp

Inventors

• Zhang Heng
• Khanpour Mehdi
• Cao Jun
• Liu Chang
• Momtaz Afshin

Classifications

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03D3/006 Primary

  by sampling the oscillations and further processing the samples, e.g. by computing techniques (H03D3/007 takes precedence) · CPC title

• H04B1/745 Primary

  using by-passing or self-healing methods · CPC title

• H03D3/02

  by detecting phase difference between two signals obtained from input signal (H03D3/28 - H03D3/32 take precedence; {muting in frequency-modulation receivers H03G3/28}; limiting arrangements H03G11/00) · CPC title