Self-organizing barrier layer disposed between a metallization layer and a semiconductor region

Patent metadata

Field	Value
Publication number	US-10332793-B2
Application number	US-201514953502-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Nov 30, 2015
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor region;
a metallization layer disposed over the semiconductor region; and
a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises an alloying element configured to be self-segregating from the metallization layer;
wherein the metallization layer comprises the alloying element in a lower concentration than the barrier layer,
wherein the self-organizing barrier layer comprises a silicide formed from the alloying element and semiconductor material of the semiconductor region, and a further barrier layer disposed between the metallization layer and the semiconductor region, the further barrier layer comprising at least one defect, the at least one defects comprising an opening extending through the further barrier layer, and wherein the self-organizing barrier layer seals the at least one defect in the further barrier layer.

2. The semiconductor device of claim 1 ,
wherein the self-organizing barrier layer is in physical contact to at least one of the metallization layer or the semiconductor region.

3. The semiconductor device of claim 1 ,
wherein a temperature activating a segregation of the alloying element from the metallization layer is less than a temperature activating a reaction of the semiconductor region with the metallization layer.

4. The semiconductor device of claim 1 ,
wherein a concentration of the alloying element in the metallization layer is in the range from about 0.5 at % to about 50 at %.

5. The semiconductor device of claim 1 ,
wherein the alloying element is at least one of: manganese, tantalum, chromium, tungsten, molybdenum.

6. The semiconductor device of claim 1 ,
wherein a thickness of the metallization layer is greater than ten times a thickness of the self-organizing barrier layer.

7. The semiconductor device of claim 1 ,
wherein the metallization layer comprises a self-segregating composition comprising the alloying element.

8. The semiconductor device of claim 7 ,
wherein a concentration of the alloying element in the metallization layer is less than a concentration of a host material in the metallization layer.

9. The semiconductor device of claim 8 ,
wherein the host material is copper.

10. The semiconductor device of claim 8 ,
wherein the metallization layer is substantially free of a semiconductor of the semiconductor region.

11. The semiconductor device of claim 1 ,
wherein a specific resistance of the metallization layer is less than 70 μOhm cm.

12. The semiconductor device of claim 1 ,
wherein the alloying element is configured to segregate from the metallization layer faster than the metallization layer chemically reacts with the semiconductor region.

13. The semiconductor device of claim 1 ,
wherein the metallization layer comprises a power metallization.

14. The semiconductor device of claim 1 , further comprising:
a contact pad formed at least one of in or over the metallization layer.

15. The semiconductor device of claim 1 , further comprising:
an electronic power semiconductor element formed at least one of in or over the semiconductor region, wherein the electronic power semiconductor element is electrically coupled with the metallization layer.

16. A semiconductor device, comprising:
a semiconductor region;
a metallization layer disposed over the semiconductor region; and
a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises an alloying element configured to be self-segregating from the metallization layer;
wherein the metallization layer comprises a host material in a concentration that is more than a concentration of the alloying element in the metallization layer and/or is lower than a concentration of the host material in the self-organizing barrier layer;
wherein the self-organizing barrier layer comprises a compound formed from the alloying element and semiconductor material of the semiconductor region and
a further barrier layer disposed between the metallization layer and the semiconductor region, the further barrier layer comprising at least one defect, the at least one defects comprising an opening extending through the further barrier layer, and wherein the self-organizing barrier layer seals the at least one defect in the further barrier layer.

17. The semiconductor device of claim 16 , wherein the compound is a silicide of the alloying element and a semiconductor of the semiconductor region.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Robl Werner
• Fugger Michael
• Schaeffer Carsten
• Nelhiebel Michael
• Pruegl Klemens

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/4424

  Copper alloys · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title