Optoelectronic devices with back contact

Patent metadata

Field	Value
Publication number	US-9305964-B1
Application number	US-201514749067-A
Country	US
Kind code	B1
Filing date	Jun 24, 2015
Priority date	Apr 1, 2015
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, said method comprising:
providing an optoelectronic device embedded within a dielectric material, wherein said optoelectronic device is located on a silicon layer or a germanium layer and in one region of a substrate, wherein an insulator layer separates said silicon layer or said germanium layer from said substrate in said first region;
forming a pair of openings within said dielectric material and between said optoelectronic device, each opening extends to a surface of said silicon layer or said germanium layer;
removing said silicon layer or said germanium layer located beneath said optoelectronic device to form an air gap; and
forming a bottom metal contact within said air gap and lining said pair of openings, wherein a portion of said bottom metal contact contacts an entire bottommost surface of said optoelectronic device.

2. The method of claim 1 , wherein a bottommost surface of said optoelectronic device is in direct contact with said germanium layer.

3. The method of claim 1 , wherein a germanium buffer layer is located between a bottommost surface of said optoelectronic device and said silicon layer, and wherein said germanium buffer layer is also removed during air gap formation.

4. The method of claim 1 , wherein said forming said pair of openings comprises lithography and etching.

5. The method of claim 1 , wherein said removing said silicon layer or said germanium layer comprises etching in a gas of XeF 2 .

6. The method of claim 1 , further comprising forming an interconnect metal structure in a remaining volume of each opening.

7. A method of forming a semiconductor structure, said method comprising:
providing an optoelectronic device embedded within a dielectric material, wherein said optoelectronic device is located on a bulk semiconductor substrate;
forming a pair of openings within said dielectric material and between said optoelectronic device, each opening extends to a surface of bulk semiconductor substrate;
removing an upper portion of said bulk semiconductor substrate that is located beneath said optoelectronic device to form an air gap; and
forming a bottom metal contact in said air gap and lining said pair of openings, wherein a portion of said bottom metal contact contacts an entire bottommost surface of said optoelectronic device.

8. The method of claim 7 , wherein a germanium buffer layer is located between a bottommost surface of said optoelectronic device and said silicon layer, and wherein said germanium buffer layer is also removed during air gap formation.

9. The method of claim 7 , further comprising forming an interconnect metal structure in a remaining volume of each opening and a remaining volume of said air gap.

Assignees

• IBM

Inventors

• Leobandung Effendi
• Li Ning
• Ning Tak H
• Plouchart Jean-Olivier
• Sadana Devendra K

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H20/032

  of electrodes · CPC title