Embedded HKMG non-volatile memory

Patent metadata

Field	Value
Publication number	US-9842848-B2
Application number	US-201514967813-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 14, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

First claim

What is claimed is:

1. A method of forming an integrated circuit (IC) comprising:
providing a substrate comprising a logic region and a memory region;
forming a first sacrificial gate stack within the logic region and a second sacrificial gate stack within the memory region;
forming a charge trapping layer over the substrate, extended along sidewalls of the first and second sacrificial gate stacks and over the first and second sacrificial gate stacks;
forming a conductive layer over the charge trapping layer having a planar upper surface;
forming a sacrificial hard mask layer on the conductive layer; and
etching the sacrificial hard mask layer by a self-aligned process to remove lateral portions of the sacrificial hard mask layer while leaving vertical portions along sidewalls of the first and second sacrificial gate stacks to form a hard mask on the conductive layer;
etching the conductive layer and the charge trapping layer according to the hard mask to form a third sacrificial gate stack alongside the second sacrificial gate stack; and
replacing the first sacrificial gate stack and at least one of the second sacrificial gate stack and the third sacrificial gate stack with a high-k gate dielectric layer and a metal layer to form a first metal gate within the logic region and a second metal gate within the memory region.

2. The method of claim 1 , wherein the memory region comprises:
a flash memory cell disposed over the substrate and comprising a select gate and a control gate separated by a charge trapping layer extending under the control gate;
wherein the second metal gate comprises the select gate.

3. The method of claim 1 , wherein the third sacrificial gate stack is replaced with the high-k gate dielectric layer and the metal layer.

4. The method of claim 1 , further comprising:
forming sidewall spacers alongside the first, second and third sacrificial gate stacks;
forming source/drain regions within the substrate; and
performing a salicidation process to form a silicide layer on upper surfaces of the source/drain regions.

5. The method of claim 4 , further comprising:
forming a contact etch stop layer lining the sidewall spacers;
forming a first inter-layer dielectric layer on the contact etch stop layer; and
performing a first planarization on the first inter-layer dielectric layer and the sidewall spacers to expose the first sacrificial gate stack within the logic region and the second sacrificial gate stack within the memory region.

6. The method of claim 5 , replacing the sacrificial gate stacks further comprising:
performing an etch to remove the first sacrificial gate stack and at least one of the second sacrificial gate stack and the third sacrificial gate stack, leaving trenches between the sidewall spacers;
filling the trenches with the high-k gate dielectric layer and the metal layer to form the first metal gate within the logic region and the second metal gate within the memory region; and
performing a second planarization on the metal layer and the high-k gate dielectric layer to form the first metal gate within the logic region and the second metal gate within the memory region.

7. The method of claim 1 , wherein forming the first and second sacrificial gate stacks comprises:
forming a gate oxide layer over the substrate;
forming a conductive sacrificial gate layer over the gate oxide layer; and
patterning and etching the conductive sacrificial gate layer to form the first sacrificial gate stack within the logic region and the second sacrificial gate stack within the memory region.

8. The method of claim 1 , wherein forming the conductive layer comprises depositing the conductive layer and performing an etch to the conductive layer to form a top surface substantially aligned with top surfaces of a conductive sacrificial gate layer the first and second sacrificial gate stacks.

9. The method of claim 1 , wherein the hard mask of the third sacrificial gate stack and the charge trapping layer have top surfaces substantially aligned.

10. A method of forming an integrated circuit (IC) comprising:
providing a substrate comprising a logic region having a logic device area and a memory region having a NVM device area;
forming a first conductive layer over the substrate; and
patterning and etching the first conductive layer to form a first sacrificial gate stack within the logic region and a second sacrificial gate stack within the memory region;
forming a charge trapping layer over the substrate, contacting sidewalls of the first conductive layer and over the first and second sacrificial gate stacks;
forming a second conductive layer over the charge trapping layer;
patterning the second conductive layer and the charge trapping layer to form a third sacrificial gate stack alongside the second sacrificial gate stack;
and
replacing the first and second sacrificial gate stacks with a high-k gate dielectric layer and a metal layer to form a first metal gate of a logic device within the logic region and a second metal gate of a NVM device within the memory region.

11. The method of claim 10 , wherein the NVM device comprises:
a flash memory cell disposed over the substrate and comprising a select gate and a control gate separated by the charge trapping layer extending under the control gate;
wherein the second metal gate comprises the select gate.

12. The method of claim 11 , wherein the third sacrificial gate stack is replaced with the high-k gate dielectric layer and the metal layer.

13. The method of claim 10 , replacing the sacrificial gate stacks further comprising:
after forming and patterning the charge trapping layer, forming sidewall spacers alongside and contacting sidewalls of the first conductive layer opposite to the patterned charge trapping layer;
performing an etch to remove the first and second sacrificial gate stacks, leaving trenches between the sidewall spacers; and
filling the trenches with the high-k gate dielectric layer and the metal layer to form the first metal gate within the logic region and the second metal gate within the memory region.

14. The method of claim 13 , wherein forming the first and second sacrificial gate stacks comprises:
forming a gate oxide layer over the substrate;
forming a polysilicon layer over the gate oxide layer;
forming a sacrificial hard mask layer over the polysilicon layer; and
patterning and etching the sacrificial hard mask layer, the polysilicon layer and the oxide layer to form the first sacrificial gate stack within the logic region and the second sacrificial gate stack within the memory region.

15. The method of claim 14 , further comprising:
forming a contact etch stop layer lining the sidewall spacers;
forming a first inter-layer dielectric layer on the contact etch stop layer; and
performing a planarization on the first inter-layer dielectric layer and the sacrificial hard mask layer to form the first metal gate within the logic region and the second metal gate within the memory region.

16. A method of forming an integrated circuit (IC), comprising:
providing a substrate comprising a logic region and a memory region;
forming a first conductive layer over the substrate;
patterning and etching the first conductive layer to form a first sacrificial gate stack within the logic region and a second sacrificial gate stack within the memory region;
forming a charge trapping layer over the substrate, contacting sidewalls of the first conductive layer and over the first and second sacrificial gate stacks;
forming a second conductive layer over the charge trapping

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Wei Cheng
• Teng Li-Feng

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L21/32115

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic