Recessed salicide structure to integrate a flash memory device with a high k, metal gate logic device

Patent metadata

Field	Value
Publication number	US-2016013198-A1
Application number	US-201414330140-A
Country	US
Kind code	A1
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. A method of manufacturing the integrated circuit is also provided.

First claim

1 . An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
a semiconductor substrate including a memory region and a logic region adjacent to the memory region; a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; a flash memory cell device arranged over the memory region, the flash memory cell device including a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions; and a silicide contact pad arranged over a top surface of the memory cell gate, wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions.

2 . The integrated circuit according to claim 1 , wherein the memory cell gate is one of a memory gate, a select gate, an erase gate, a word line, and a control gate.

3 . The integrated circuit according to claim 1 , wherein the flash memory cell device includes:
a select gate; a memory gate spaced from the memory gate; and a charge trapping dielectric arranged under the memory gate and between neighboring sidewalls of the select and memory gates; wherein the memory cell gate is the select gate or the memory gate, and one of the dielectric regions includes the charge trapping dielectric.

4 . The integrated circuit according to claim 1 , wherein the flash memory cell device includes:
a floating gate; an erase gate and a word line spaced from the floating gate on opposite sides of the floating gate; a control gate arranged over the floating gate; and a floating gate spacer arranged between neighboring sidewalls of the control gate, the word line, and the erase gate; wherein the memory cell gate is the floating gate or the erase gate, and one of the dielectric regions includes the floating gate spacer.

5 . The integrated circuit according to claim 1 , wherein at least one of:
the top surface of the memory cell gate is recessed about 10-500 Angstroms (A) below the top surface of the metal gate; and the top surface of the memory cell gate is recessed about 100-300 A below the top surfaces of the dielectric regions.

6 . The integrated circuit according to claim 1 , wherein
the top surface of the silicide contact pad is recessed about 50-100 Angstroms below the top surfaces of the dielectric regions.

7 . The integrated circuit according to claim 1 , wherein the top surface of the memory cell gate is substantially planar or the top surface of the silicide contact pad is substantially planar.

8 . The integrated circuit according to claim 1 , wherein the top surfaces of the dielectric regions are recessed below the top surface of the metal gate.

9 . The integrated circuit according to claim 1 , further including:
a dielectric mask at least partially covering the logic region, while leaving the memory region uncovered.

10 - 19 . (canceled)

20 . An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
a semiconductor substrate including a memory region and a logic region adjacent to the memory region, the memory region including a common source/drain region and a pair of individual source/drain regions arranged on opposite sides of the common source/drain region; a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; and a pair of flash memory cell devices arranged over the memory region, wherein each flash memory cell device corresponds to one of the individual source/drain regions and includes:
a select gate and a memory gate arranged between the common source/drain region and the corresponding individual source/drain region; and
a charge trapping dielectric arranged between neighboring sidewalls of the memory and select gates, and arranged under the memory gate; and
silicide contact pads respectively arranged over top surfaces of the select and memory gates, wherein top surfaces of the silicide contact pads are recessed relative to a top surface of the metal gate and top surfaces of the charge trapping dielectrics

21 . The integrated circuit according to claim 20 , wherein at least one of:
the top surfaces of the select and memory gates are recessed about 10-500 Angstroms (A) below the top surface of the metal gate; and the top surfaces of the select and memory gates are recessed about 100-300 A below the top surfaces of the charge trapping dielectrics.

22 . The integrated circuit according to claim 20 , wherein the top surfaces of the select and memory gates are substantially planar, and the top surfaces of the silicide contact pads are substantially planar.

23 . The integrated circuit according to claim 20 , wherein the top surfaces of the charge trapping dielectrics are recessed below the top surface of the metal gate.

24 . The integrated circuit according to claim 20 , further including:
a dielectric mask at least partially covering the logic region, while leaving the memory region uncovered.

25 . An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
a flash memory cell device arranged over a semiconductor substrate, the flash memory cell device including a memory cell gate electrically insulated on opposing sides by corresponding dielectric layers; and a silicide contact pad arranged over a top surface of the memory cell gate, wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to top surfaces of the dielectric layers.

26 . The integrated circuit according to claim 25 , further comprising:
a logic device arranged over the semiconductor substrate and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding about 3.9; wherein the top surfaces of the memory cell gate and the silicide contact pad are recessed relative to a top surface of the metal gate.

27 . The integrated circuit according to claim 26 , wherein the top surfaces of the dielectric layers are recessed below the top surface of the metal gate.

28 . The integrated circuit according to claim 26 , further comprising:
a dielectric mask covering the logic device, while leaving the flash memory cell device uncovered; and an interlayer dielectric (ILD) layer covering the dielectric mask and the flash memory cell device.

29 . The integrated circuit according to claim 25 , wherein the flash memory cell device includes:
an erase gate arranged over a first source/drain region of the semiconductor substrate; a wordline arranged between the first source/drain region and a second source/drain region of the semiconductor substrate; a floating gate arranged between the wordline and the erase gate; a control gate arranged over the floating gate; and dielectric layers arranged on opposing sides of the erase gate, the wordline, the floating gate, and the control gate; and wherein the memory cell gate is one of the wordline, the erase gate, and the control gate.

30 . The integrated circuit according to claim 25 , wherein the flash memory cell device includes:
a select gate arranged between first and second source/drain regions of the semiconductor substrate; a memory gate arranged between the select gate and the second source/

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Ming Chyi

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/696 Primary

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title