Systems and methods for reduced program disturb for 3D NAND flash

Patent metadata

Field	Value
Publication number	US-9373409-B2
Application number	US-201414326212-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.

First claim

What is claimed is:

1. A memory device, comprising:
an array structure of memory cells, the array structure organized into a plurality of even pages, a plurality of odd pages, and a plurality of rows that are perpendicular to the even and odd pages, such that each row includes a first plurality of memory cells located on the even pages and a second plurality of memory cells located on the odd pages;
a first string select structure at a first side of the array structure and connected to the even pages;
a second string select structure at a second side of the array structure opposite the first side, the second string select structure connected to the odd pages; and
a controller operably connected to the array structure and to the first and second string select structures,
wherein the controller is operable to program the even pages, beginning with the first plurality of memory cells in a first row closest to the first side,
wherein the controller is further operable to program the odd pages, beginning with the second plurality of memory cells in a last row farthest from the first side,
wherein all of the memory cells in the first plurality of memory cells in the first row are programmed substantially simultaneously during a first time period,
wherein all of the memory cells in the second plurality of memory cells in the last row are programmed substantially simultaneously during a second time period; and
wherein the second time period is substantially immediately after the first time period, and the first and second pluralities of memory cells are alternately programmed.

2. The memory device of claim 1 , wherein the controller is further operable to program the first plurality of memory cells that are associated with even pages in every row before the controller begins programming the odd pages.

3. The memory device of claim 1 , wherein the controller is further operable to program the second plurality of memory cells that are associated with odd pages in every row before the controller begins programming the even pages.

4. The memory device of claim 1 , wherein each memory cell in the first plurality of memory cells is individually programmed, such that when a memory cell within the first plurality of memory cells is programmed, programming is inhibited for a remainder of memory cells within the first plurality of memory cells.

5. The memory device of claim 1 , wherein all of the memory cells in the first plurality of memory cells in the first row are programmed substantially simultaneously during a first time period.

6. The memory device of claim 5 , wherein programming is inhibited on the odd pages during the first time period.

7. The memory device of claim 1 , wherein the array structure is a 3D NAND Flash array structure.

8. The memory device of claim 1 , wherein the memory cells are multi-level cells that each store more than one bit of information.

9. A method for programming memory cells in an array structure, the array structure organized into a plurality of even pages, a plurality of odd pages, and a plurality of rows that are perpendicular to the even and odd pages, such that each row includes a first plurality of memory cells located on the even pages and a second plurality of memory cells located on the odd pages, the method comprising:
selecting the even pages with a first string select structure provided at a first side of the array structure and connected to the even pages, the first string select structure being closest to a first row;
programming, by a controller, the even pages, beginning with the first plurality of memory cells in the first row;
selecting the odd pages with a second string select structure provided at a second side of the array structure and connected to the odd pages, the second string select structure being closest to a last row; and
programming, by the controller, the odd pages, beginning with the second plurality of memory cells in the last row;
wherein the programming occurs substantially simultaneously for all of the memory cells in the first plurality of memory cells in the first row during a first time period;
wherein the programming occurs substantially simultaneously for all of the memory cells in the second plurality of memory cells in the last row during a second time period; and
wherein the second time period is substantially immediately after the first time period, and the first and second pluralities of memory cells are alternately programmed.

10. The method of claim 9 , wherein the first pluralities of memory cells in every row are programmed before the programming of the odd pages.

11. The method of claim 9 , wherein the second pluralities of memory cells in every row are programmed before the programming of the even pages.

12. The method of claim 9 , wherein each memory cell in the first plurality of memory cells is individually programmed, such that when a memory cell within the first plurality of memory cells is programmed, programming is inhibited for a remainder of memory cells within the first plurality of memory cells.

13. The method of claim 9 , wherein the programming occurs substantially simultaneously for all of the memory cells in the first plurality of memory cells in the first row during a first time period.

14. The method of claim 13 , wherein programming is inhibited on the odd pages during the first time period.

15. The method of claim 9 , wherein the array structure is a 3D NAND Flash array structure.

16. The method of claim 9 , wherein the memory cells are multi-level cells that each store more than one bit of information.

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Kuo-Pin
• Chang Chih-Shen

Classifications

• G11C2211/5648

  Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant · CPC title

• G11C2211/5622

  Concurrent multilevel programming of more than one cell · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title