Semiconductor memory device including dummy memory cells and method of operating the same

Patent metadata

Field	Value
Publication number	US-9679657-B2
Application number	US-201614988518-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	May 15, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A method of operating a semiconductor memory device including a plurality of cell strings coupled to dummy word lines and normal word lines includes performing a first sub-program operation on selected normal memory cells by sequentially applying first program pulses to a selected normal word line and performing a second sub-program operation on the selected normal memory cells by sequentially applying second program pulses greater than the first program pulses to the selected normal word line, wherein at least one of the dummy word lines is biased in a same manner as the selected normal word line whenever each of the first program pulses is applied to the selected normal word line.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device including a plurality of cell strings coupled to dummy word lines and normal word lines, the method comprising:
performing a first sub-program operation on selected normal memory cells by sequentially applying first program pulses to a selected normal word line; and
performing a second sub-program operation on the selected normal memory cells by sequentially applying second program pulses having a higher voltage level than the first program pulses to the selected normal word line,
wherein the first program pulses are applied to at least one of the dummy word lines when the first program pulses are applied to the selected normal word line.

2. The method of claim 1 , wherein the at least one of the dummy word lines is biased to a program pass pulse lower than the second program pulses whenever each of the second program pulses are applied to the selected normal word line.

3. The method of claim 2 , wherein unselected normal word lines are biased to the program pass pulse whenever each of the second program pulses are applied to the selected normal word line.

4. The method of claim 1 , wherein unselected normal word lines are biased to a program pass pulse lower than the first program pulses whenever each of the first program pulses are applied to the selected normal word line.

5. The method of claim 1 , wherein the at least one of the dummy word lines is adjacent to the selected normal word line.

6. The method of claim 1 , wherein the selected normal word line is adjacent to the at least one of the normal word lines.

7. The method of claim 1 , wherein the first program pulses are gradually increased by a first step voltage,
a lowest program pulse, among the second program pulses, has a higher voltage level than a highest program pulse, among the first program pulses, by a second step voltage, and
the second step voltage is lower than the first step voltage.

8. The method of claim 7 , wherein the second program pulses are gradually increased by the first step voltage.

9. The method of claim 1 , wherein the performing of the first sub-program operation comprises:
applying one of the first program pulses to the selected normal word line to perform the first sub-program operation;
determining whether the selected normal memory cells correspond to a program pass by performing a first program verify on the selected normal memory cells by applying a sub-verify voltage to the selected normal word line; and
repeating the first sub-program and the first program verify until the selected normal memory cells correspond to the program pass.

10. The method of claim 9 , wherein the performing the second sub-program operation comprises:
applying one of the second program pulses to the selected normal word line;
determining whether the selected normal memory cells correspond to the program pass by performing a second program verify on the selected normal memory cells by applying a target verify voltage to the selected normal word line; and
repeating the second sub-program and the second program verify until the selected normal memory cells correspond to the program pass,
wherein the sub-verify voltage is lower than the target verify voltage.

11. The method of claim 1 , wherein each of the plurality of cell strings comprises:
dummy memory cells coupled to the dummy word lines;
normal memory cells coupled to the normal word lines; and
a drain selection transistor coupled between the dummy memory cells and a bit line,
wherein the drain selection transistor, the dummy memory cells and the normal memory cells are coupled in series.

12. The method of claim 1 , wherein each of the plurality of cell strings comprises:
dummy memory cells coupled to the dummy word lines;
normal memory cells coupled to the normal word lines; and
a source selection transistor coupled between the dummy memory cells and a common source line,
wherein the source selection transistor, the dummy memory cells and the normal memory cells are coupled in series.

13. The method of claim 1 , wherein the normal word lines are divided into first normal word lines and second normal word lines, and
wherein each of the plurality of cell strings comprises:
first normal memory cells coupled to the first normal word lines and second normal memory cells coupled to the second normal word lines;
a pipe transistor coupled to a pipe line; and
dummy memory cells coupled to the dummy word lines,
wherein a first dummy memory cell, among the dummy memory cells, is coupled between the first normal memory cells and the pipe transistor, and
a second dummy memory cell, among the dummy memory cells, is coupled between the second normal memory cells and the pipe transistor.

14. The method of claim 1 , wherein each of the plurality of cell strings comprises:
first normal memory cells coupled to first normal word lines;
second normal memory cells coupled to second normal word lines; and
dummy memory cells coupled to the dummy word lines,
wherein at least one of the dummy memory cells is coupled between the first normal memory cells and the second normal memory cells.

15. A semiconductor memory device, comprising:
a memory cell array including dummy memory cells coupled to dummy word lines and normal memory cells coupled to normal word lines; and
a peripheral circuit performing first sub-programs on selected normal memory cells by applying first program pulses to a selected normal word line and performing second sub-programs on the selected normal memory cells by applying second program pulses to the selected normal word line during a program operation,
wherein the peripheral circuit applies the first program pulses to a selected dummy word line when the first program pulses are applied to the selected normal word line.

16. The semiconductor memory device of claim 15 , wherein the peripheral circuit controls the voltage of the selected dummy word line during each of the second sub-programs in the same manner as an unselected normal word line, among the normal word lines.

Assignees

• Sk Hynix Inc

Inventors

• Park Kyoung Jin
• Bae Sung Ho
• Han Byeong Il

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/12 Primary

  Programming voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title