Semiconductor memory device and operating method thereof with a connection control transistor operation voltage adjusted

Patent metadata

Field	Value
Publication number	US-10020057-B2
Application number	US-201615250841-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Mar 29, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

There is provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation by applying a program voltage, a pass voltage, and a pipe transistor operation voltage, to the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform the program operation, wherein the control logic adjusts a potential level of the pipe transistor operation voltage according to an address of a selected page among the plurality of pages.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of pages;
a peripheral circuit suitable for performing a program operation by applying a program voltage, a pass voltage, and a connection control transistor operation voltage, to the memory cell array; and
a control logic suitable for controlling the peripheral circuit to perform the program operation,
wherein the control logic adjusts a potential level of the connection control transistor operation voltage,
wherein the memory cell array includes a plurality of strings, and
wherein each of the plurality of strings comprises:
a plurality of memory cells vertically stacked along a U-shaped channel layer, the plurality of memory cells comprising drain-side memory cells and source-side memory cells;
a drain select transistor and a source select transistor provided on both ends of the U-shaped channel layer, respectively; and
a connection control transistor arranged at a lowermost portion of the U-shaped channel layer and controlled by the connection control transistor operation voltage, wherein the connection control transistor couples the drain-side memory cells and the source-side memory cells while the connection control transistor operation voltage is adjusted according to an address of a selected page among the plurality of pages while a level of the pass voltage is not adjusted according to the address of the selected page among the plurality of pages.

2. The semiconductor memory device of claim 1 , wherein memory cells coupled to the same word line among the plurality of memory cells included in the memory cell array are included in one page among the plurality of pages.

3. The semiconductor memory device of claim 2 , wherein channel boosting levels of strings in a program prohibition mode among the plurality of strings are adjusted according to the connection control transistor operation voltage.

4. The semiconductor memory device of claim 1 ,
wherein a string among the strings including the drain-side memory cells is coupled between a bit line and the connection control transistor, and a string among the strings including the source-side memory cells is coupled between a source line and the connection control transistor.

5. The semiconductor memory device of claim 1 , wherein the connection control transistor operation voltage is applied to the connection control transistor.

6. The semiconductor memory device of claim 4 , wherein the control logic controls the peripheral circuit such that memory cells are sequentially programmed from memory cells adjacent to the source select transistor to memory cells adjacent to the drain select transistor.

7. The semiconductor memory device of claim 1 , wherein the control logic controls the potential level of the connection control transistor operation voltage to increase as the selected page becomes close to the drain select transistor.

8. The semiconductor memory device of claim 6 , wherein the control logic:
controls the peripheral circuit to set the connection control transistor operation voltage to a first potential level when memory cells of the selected page included in the drain-side memory cells; and
controls the peripheral circuit to set the connection control transistor operation voltage to a second potential level lower than the first potential level when the memory cells of the selected page are included in the source-side memory cells.

9. The semiconductor memory device of claim 4 , wherein the control logic controls the peripheral circuit such that memory cells are sequentially programmed from memory cells adjacent to the drain select transistor to memory cells adjacent to the source select transistor.

10. The semiconductor memory device of claim 9 , wherein the control logic controls the potential level of the connection control transistor operation voltage to decrease as the selected page becomes close to the drain select transistor.

11. The semiconductor memory device of claim 9 , wherein the control logic:
controls the peripheral circuit to set the connection control transistor operation voltage to a first potential level when memory cells of the selected page included in the drain-side memory cells; and
controls the peripheral circuit to set the connection control transistor operation voltage to a second potential level higher than the first potential level when the memory cells of the selected page are included in the source-side memory cells.

12. A semiconductor memory device comprising:
a plurality of strings including a plurality of memory cells coupled in series between a bit line and a source line;
a peripheral circuit suitable for performing a program operation by applying to the plurality of strings a program voltage, a pass voltage, and a connection control transistor operation voltage; and
a control logic suitable for controlling the peripheral circuit to perform the program operation,
wherein the control logic adjusts a potential level of the connection control transistor operation voltage, and
wherein each of the plurality of strings comprises:
the plurality of memory cells vertically stacked along a U-shaped channel layer, the plurality of memory cells comprising drain-side memory cells and source-side memory cells;
a drain select transistor and a source select transistor provided on both ends of the U-shaped channel layer, respectively; and
a connection control transistor arranged at a lowermost portion of the U-shaped channel layer and controlled by the connection control transistor operation voltage, wherein the connection control transistor couples the drain-side memory cells and the source-side memory cells, and the connection control transistor operation voltage is adjusted according to a program order of a selected memory cell among the plurality of memory cells while a level of the pass voltage is not adjusted according to the program order of the selected memory cell among the plurality of memory cells.

13. The semiconductor memory device of claim 12 , wherein the control logic:
controls the peripheral circuit to sequentially program the plurality of memory cells according to the program order; and
controls the peripheral circuit so that the connection control transistor operation voltage is adjusted according to the program order of the selected memory cell.

14. The semiconductor memory device of claim 12 , wherein channel potential levels of strings in a program prohibition mode among the plurality of strings are adjusted according to the potential level of the connection control transistor operation voltage.

15. The semiconductor memory device of claim 12 , wherein a string among the strings including the drain-side memory cells is coupled between the bit line and the connection control transistor, and a string among the strings including the source-side memory cells is coupled between the source line and the connection control transistor.

16. A method of operating a semiconductor memory device comprising a plurality of strings including a plurality of drain-side memory cells and a plurality of source-side memory cells vertically stacked along a U-shaped channel layer, a drain select transistor and a source select transistor provided on both ends of the U-shaped channel layer, respectively, and a connection control transistor provided at a lowermost portion of the U-shaped channel layer to couple the drain-side memory cells and the source-side memory cells, the method comprising:
setting a potential level of a connection control transistor operation voltage according to positions

Assignees

• Sk Hynix Inc

Inventors

• Park Jong Kyung
• Seo Ji Hyun

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title