Structures to avoid floating resurf layer in high voltage lateral devices

Patent metadata

Field	Value
Publication number	US-10319809-B2
Application number	US-201715843444-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Feb 28, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;

a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and
a vertical shunt of p-type semiconductor material disposed in the substrate, the vertical shunt extending vertically through an opening in the drain drift region, from the RESURF layer to the p-type semiconductor material below the drain drift region.

2. The semiconductor device of claim 1 , wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

3. The semiconductor device of claim 1 , wherein a width of the vertical shunt is 3 microns to 8 microns.

4. The semiconductor device of claim 1 , wherein a length of the vertical shunt is 3 microns to 10 microns.

5. The semiconductor device of claim 1 , wherein the vertical shunt is laterally separated from the body by less than 3 microns.

6. The semiconductor device of claim 1 , comprising a plurality of instances of the vertical shunt.

7. The semiconductor device of claim 1 , wherein a resistance of the vertical shunt is 5000 to 50000 ohms.

8. A semiconductor device, comprising:
a semiconductor substrate comprising p-type material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the semiconductor substrate; and
a drain drift region of n-type semiconductor material disposed in the semiconductor substrate, the drain drift region extending laterally to the body;

a doped layer of p-type semiconductor material disposed in the semiconductor substrate over at least a portion of the drain drift region, the doped layer extending from the drain drift region to a top surface of the semiconductor substrate; and
a vertical shunt of p-type semiconductor material disposed in the semiconductor substrate, the vertical shunt extending vertically through an opening in the drain drift region, between the doped layer and a p-type portion of the semiconductor substrate below the drain drift region.

9. The semiconductor device of claim 8 , wherein the doped layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

10. The semiconductor device of claim 8 , wherein a width of the vertical shunt is 3 microns to 8 microns.

11. The semiconductor device of claim 8 , wherein a length of the vertical shunt is 3 microns to 10 microns.

12. The semiconductor device of claim 8 , wherein the vertical shunt is laterally separated from the body by less than 3 microns.

13. The semiconductor device of claim 8 , comprising a plurality of instances of the vertical shunt.

14. A semiconductor device, comprising:
a semiconductor substrate comprising p-type material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the semiconductor substrate;
a source region within the body;
a drain drift region of n-type semiconductor material disposed in the semiconductor substrate, the drain drift region extending laterally to the body; and
a gate extending over a portion of the body region and a portion of the drain drift region;

an oxide region at a portion of a top surface of the semiconductor substrate;
a doped layer of p-type semiconductor material disposed in the semiconductor substrate over at least a portion of the drain drift region, the doped layer extending from the drain drift region to the top surface of the semiconductor substrate under the oxide region;
a vertical shunt of p-type semiconductor material disposed in the semiconductor substrate, the vertical shunt extending vertically through an opening in the drain drift region, between the doped layer and a p-type portion of the semiconductor substrate below the drain drift region;
an n-type buried layer in the semiconductor substrate below the body; and
an n-type sinker in the semiconductor substrate, the n-type buried layer extending from the drain drift region to the n-type sinker, the n-type buried layer and n-type sinker isolating the body from a portion of the semiconductor substrate below the n-type buried layer.

15. The semiconductor device of claim 14 , wherein the doped layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

16. The semiconductor device of claim 15 , wherein a width of the vertical shunt is 3 microns to 8 microns.

17. The semiconductor device of claim 16 , wherein a length of the vertical shunt is 3 microns to 10 microns.

18. The semiconductor device of claim 17 , wherein the vertical shunt is laterally separated from the body by less than 3 microns.

19. The semiconductor device of claim 18 , comprising a plurality of instances of the vertical shunt.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Hower Philip L
• Lin John
• Mathur Guru
• Balster Scott G
• Bulucea Constantin
• Lee Zachary K
• Pendharkar Sameer P

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L29/7816

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L23/485

  Electricity · mapped topic