Apparatuses and methods for timing domain crossing

Patent metadata

Field	Value
Publication number	US-10120647-B2
Application number	US-201715690085-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	May 12, 2014
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

First claim

What is claimed is:

1. An apparatus comprising:
an input circuit configured to latch an input signal to provide an intermediate signal;
an output circuit configured to provide an output signal responsive to the intermediate signal and a clock signal; and
a pulse generator circuit including a delay circuit and configured to provide a feedback pulse based, at least in part, on the output signal;
wherein the input circuit is configured to reset latching the input signal responsive to the feedback pulse,
wherein the pulse generator circuit is configured to provide the feedback pulse based only on the output signal, and
wherein the pulse generator circuit is configured to produce one of rising and trailing edges of the feedback pulse responsive to one of rising and trailing edges of the output signal and produce the other of rising and trailing edges of the feedback pulse responsive to a delayed one of rising and trailing edges of the output signal.

2. The apparatus of claim 1 , wherein the input signal is provided asynchronously to the clock signal and the output circuit is configured to provide the output signal in synchronism with the clock signal.

3. An apparatus comprising:
an input circuit configured to latch an input signal to provide an intermediate signal;
an output circuit configured to provide an output signal responsive to the intermediate signal and a clock signal; and
a pulse generator circuit including a delay circuit and configured to provide a feedback pulse based, at least in part, on the output signal;
wherein the input circuit is configured to reset latching the input signal responsive to the feedback pulse, and
wherein the pulse generator circuit is configured to produce one of rising and trailing edges of the feedback pulse responsive to the intermediate signal and the other of rising and trailing edges of the feedback pulse responsive to the output signal.

4. An apparatus comprising:
an input circuit configured to latch an input signal to provide an intermediate signal;
an output circuit configured to provide an output signal responsive to the intermediate signal and a clock signal; and
a pulse generator circuit including a delay circuit and configured to provide a feedback pulse based, at least in part, on the output signal;
wherein the input circuit is configured to reset latching the input signal responsive to the feedback pulse, and
wherein the pulse generator circuit is configured to provide the feedback pulse regardless of the output signal when the pulse generator circuit receives a power-up-reset signal.

5. An apparatus comprising:
a signal input terminal;
a signal output terminal;
a clock input terminal;
a RS latch circuit including a set node coupled to the signal input terminal, and further including a reset node and a first output node;
an output latch circuit including a first input node coupled to the first output node and a clock node coupled to the clock input terminal, the output latch further including a second output node; and
a pulse generator circuit including a delay circuit, and further including a second input node coupled to the second output node and a third output node coupled to the reset node,
wherein the pulse generator circuit includes a third input node coupled to the first output node.

6. The apparatus of claim 5 , wherein the pulse generator circuit includes an AND logic circuit, two inputs of the AND logic circuit are coupled to the second input node and the third input node, respectively, and an output of the AND logic circuit is coupled to the third output node.

7. The apparatus of claim 5 , wherein the pulse generator circuit includes an AND logic circuit;
wherein an input of the delay circuit is coupled to the second input node and an output of the delay circuit is coupled to one of two inputs of the AND logic circuit; and
wherein another of two inputs of the AND logic circuit is coupled to the second input node and an output of the AND logic circuit is coupled to the third output node.

8. The apparatus of claim 5 , wherein the signal input terminal is configured to receive an input signal activated during a first period of time and the signal output terminal is configured to be supplied with an output signal activated during a second period of time longer than the first period of time.

9. The apparatus of claim 5 , wherein the clock input terminal is supplied with a clock signal and the output latch circuit is configured to provide a signal to the signal output terminal in synchronism with the clock signal.

10. An apparatus comprising:
an input circuit configured to latch an input signal to provide an intermediate signal;
an output circuit configured to provide an output signal responsive to the intermediate signal and a clock signal; and
a pulse generator circuit configured to provide a feedback pulse based only on the output signal and further configured to produce one of rising and trailing edges of the feedback pulse responsive to one of rising and trailing edges of the output signal and produce the other of rising and trailing edges of the feedback pulse responsive to a delayed one of rising and trailing edges of the output signal;
wherein the input signal is provided asynchronously to the dock signal and the output circuit is configured to provide the output signal in synchronism with the clock signal; and
wherein the input circuit is configured to reset latching the input signal responsive to the feedback pulse.

11. An apparatus comprising:
an input circuit configured to latch an input signal to provide an intermediate signal;
an output circuit configured to provide an output signal responsive to the intermediate signal and a clock signal; and
a pulse generator circuit configured to provide a feedback pulse based, at least in part, on the output signal, wherein the pulse generator circuit is configured to produce one of rising and trailing edges of the feedback pulse responsive to the intermediate signal and the other of rising and trailing edges of the feedback pulse responsive to the output signal;
wherein the input circuit is configured to reset latching the input signal responsive to the feedback pulse.

12. An apparatus comprising:
a signal input terminal;
a signal output terminal;
a clock input terminal;
a RS latch circuit including a set node coupled to the signal input terminal, and further including a reset node and a first output node;
an output latch circuit including a first input node coupled to the first output node and a clock node coupled to the clock input terminal, the output latch further including a second output node; and
a pulse generator circuit including a second input node coupled to the second output node and a third output node coupled to the reset node, and further including a third input node coupled to the first output node.

13. The apparatus of claim 12 , wherein the pulse generator circuit includes an AND logic circuit, two inputs of the AND logic circuit are coupled to the second input node and the third input node, respectively, and an output of the AND logic circuit is coupled to the third output node.

14. An apparatus comprising:
a signal input terminal;
a signal output terminal;
a clock input terminal;
a RS latch circuit including a set node coupled to the signal input terminal, and further including a reset node and a first output node;
an output latch circuit including a first input node coupled to the first output node and a clock node coupled to the clock input terminal, the output latch further including a second output node; and
a pulse generator circuit including a secon

Assignees

• Micron Technology Inc

Inventors

• Huber Brian
• Howe Gary

Classifications

• G06F5/06 Primary

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title