Apparatuses and methods for timing domain crossing

Patent metadata

Field	Value
Publication number	US-9778903-B2
Application number	US-201414573215-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	May 12, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

First claim

What is claimed is:

1. An apparatus, comprising:
a timing domain transfer circuit configured to receive an event from a first timing domain, provide the event to a second timing domain, and further configured to mark the event as transferred based on the event being transferred to the second timing domain.

2. The apparatus of claim 1 , wherein the timing domain transfer circuit is further configured to verify the transfer of the event to the second timing domain based on feedback.

3. The apparatus of claim 2 , wherein the feedback comprises two separate feedback signals.

4. The apparatus of claim 3 , wherein the two separate feedback signals includes the output of the timing domain transfer circuit and an intermediate event of the timing domain transfer circuit.

5. The apparatus of claim 1 , wherein the timing domain transfer circuit comprises an input latch configured to receive the event and a feedback signal and wherein the input latch is further configured to output an intermediate event.

6. The apparatus of claim 5 , wherein the feedback signal is based on the intermediate event and the output.

7. The apparatus of claim 6 , wherein the timing domain transfer circuit further comprises a pulse generator circuit configured to generate the feedback signal based on the intermediate event and the output.

8. The apparatus of claim 7 , wherein the pulse generator circuit is configured to delay the intermediate event in relation to the output signal.

9. The apparatus of claim 1 , wherein the timing domain transfer circuit comprises an output latch configured to receive an intermediate event and configured to output the event into the second timing domain and provide the output as feedback.

10. An apparatus, comprising:
an event input line to receive an event signal from a first timing domain;
an event output line to output the event signal to a second timing domain; and
a timing domain transfer circuit configured to accept an event signal from a first timing domain and to provide the event to a second timing domain, the timing domain transfer circuit further configured to transfer the event from the first timing domain to the second timing domain and further configured to determine that the event has been transferred to the second timing domain before an input of the timing domain transfer circuit is reset, the timing domain transfer circuit comprising:
an input latch configured to receive the event and output an intermediate event signal and configured to be reset responsive to a feedback pulse;
an output latch configured to receive the intermediate event signal and configured to provide the event signal to the second timing domain; and
a pulse generator circuit configured to provide the feedback pulse based, at least in part, on the event signal from the output latch.

11. The apparatus of claim 10 , wherein the pulse generator circuit is further configured to delay the intermediate event signal in relation to the event signal provided by the output latch before providing the feedback pulse to the input latch.

12. The apparatus of claim 10 , wherein the input latch comprises an RS latch configured to be reset responsive to the feedback signal.

13. The apparatus of claim 10 , wherein the output latch comprises a master/slave flip-flop.

14. The apparatus of claim 10 , wherein the input latch comprises two NAND circuits.

15. The apparatus of claim 10 , wherein the pulse generator is configured to provide the feedback pulse based on the event signal from the output latch and the intermediate event signal.

16. The apparatus of claim 10 , wherein the pulse generator is configured to provide the feedback pulse with delay to ensure that the event signal is transferred to the second timing domain.

17. A method to transfer an event from one timing domain to another, comprising:
receiving an event in based in a first timing domain at a first latch;
receiving an intermediate event from the first latch by a second latch;
outputting an event out into a second timing domain by the second latch, wherein the event out is equal to the event in; and
resetting the first latch based on feedback.

18. The method of claim 17 , further comprising:
delaying the intermediate event; and
generating a pulse based on the delayed intermediate event and the output event.

19. The method of claim 18 , wherein the pulse is the feedback.

20. The method of claim 17 , wherein the resetting the first latch based on the feedback determines that the event was both received and transferred to the second timing domain.

Assignees

• Micron Technology Inc

Inventors

• Huber Brian
• Howe Gary

Classifications

• G06F5/06 Primary

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title