High-speed interface apparatus and deskew method thereof

Patent metadata

Field	Value
Publication number	US-10313101-B2
Application number	US-201816113857-A
Country	US
Kind code	B2
Filing date	Aug 27, 2018
Priority date	Feb 13, 2014
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

First claim

What is claimed is:

1. A device comprising:
a transmitter configured to sequentially transmit a deskew synchronous code and test data, and configured to sequentially transmit a normal synchronous code and normal data,
wherein a pattern of the deskew synchronous code is different from a pattern of the normal synchronous code, and
the deskew synchronous code includes 8-bit serial data “11111111”.

2. The device of claim 1 , wherein the normal synchronous code includes 8-bit serial data “00011101”.

3. The device of claim 1 , wherein the test data includes 8-bit serial data “01010101”.

4. The device of claim 1 , wherein the transmitter is an application processor.

5. The device of claim 1 , wherein the transmitter is an image sensor.

6. The device of claim 1 , wherein the transmitter is configured to transmit differential signals as the normal data.

7. The device of claim 1 , wherein the normal data is image data.

8. The device of claim 1 , wherein the transmitter includes:
a first transmission channel unit configured to transmit the deskew synchronous code and the test data through a first channel; and
a second transmission channel unit configured to transmit the deskew synchronous code and the test data through a second channel.

9. The device of claim 8 , wherein the transmitter includes a clock generator configured to transmit a clock signal through a clock channel.

10. The device of claim 9 , wherein each of the first channel, the second channel, and the clock channel includes two lines.

11. A device comprising:
a receiver configured to sequentially receive a deskew synchronous code and test data, and configured to sequentially receive a normal synchronous code and normal data,
wherein a pattern of the deskew synchronous code is different from a pattern of the normal synchronous code, and
the deskew synchronous code includes 8-bit serial data “11111111”.

12. The device of claim 11 , wherein the normal synchronous code includes 8-bit serial data “00011101”.

13. The device of claim 11 , wherein the test data includes 8-bit serial data “01010101”.

14. The device of claim 11 , wherein the receiver is an application processor.

15. The device of claim 11 , wherein the receiver is a display serial interface device.

16. The device of claim 11 , wherein the receiver s configured to receive differential signals as the normal data.

17. The device of claim 11 , wherein the receiver includes:
a first reception channel unit configured to receive the deskew synchronous code and the test data through a first channel; and
a second reception channel unit configured to receive the deskew synchronous code and the test data through a second channel.

18. The device of claim 17 , wherein the receiver includes a clock receiving unit configured to receive a clock signal through a clock channel.

19. The device of claim 18 , wherein each of the first channel, the second channel, and the clock channel includes two lines.

20. An application processor comprising:
a transmitter D-PHY module configured to transmit a first normal synchronous code through a first channel and to transmit a first clock signal through a first clock channel; and
a receiver D-PHY module configured to receive a second normal synchronous code through a second channel and to receive a second clock signal through a second clock channel,
wherein the first normal synchronous code includes 8-bit serial data “00011101”.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Han Soo
• Kim Sung Jun
• Kim Chae Ryung
• Park Dong Uk
• Chung Youn Woong
• Choi Jung Myung
• Lim Han Kyul
• Cha Gyeong Han

Classifications

• H04L7/0041 Primary

  Delay of data signal · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title