High-speed interface apparatus and deskew method thereof

Patent metadata

Field	Value
Publication number	US-9832005-B2
Application number	US-201615007367-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Feb 13, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

First claim

What is claimed is:

1. A high-speed data transmitter comprising:
a transmitter configured to sequentially transmit a deskew synchronous code and test data, and configured to sequentially transmit a normal synchronous code and normal data,
wherein the deskew synchronous code has a different pattern than the normal synchronous code, and the normal synchronous code includes 8-bit serial data “00011101”.

2. The high-speed data transmitter of claim 1 , wherein the high-speed data transmitter is an application processor.

3. The high-speed data transmitter of claim 1 , wherein the high-speed data transmitter is an image sensor.

4. The high-speed data transmitter of claim 3 , wherein the test data includes 8-bit serial data “01010101”.

5. The high-speed data transmitter of claim 3 , wherein the deskew synchronous code includes 8-bit serial data “11111111”.

6. The high-speed data transmitter of claim 5 , wherein the transmitter is configured to transmit differential signals as the normal data.

7. The high-speed data transmitter of claim 5 , wherein the transmitter further comprises:
a third transmission channel unit configured to transmit a third part of the deskew synchronous code and a third part of the test data through a third channel; and
a fourth transmission channel unit configured to transmit a fourth part of the deskew synchronous code and a fourth part of the test data through a fourth channel.

8. The high-speed data transmitter of claim 5 , wherein the normal data is image data.

9. A high-speed data receiver comprising:
a receiver configured to sequentially receive a deskew synchronous code and test data, and configured to sequentially receive a normal synchronous code and normal data,
wherein the deskew synchronous code has a different pattern than the normal synchronous code, and the normal synchronous code includes 8-bit serial data “00011101”.

10. The high-speed data receiver of claim 9 , wherein the high-speed data receiver is an application processor.

11. The high-speed data receiver of claim 9 , wherein the high-speed data receiver is a display serial interface device.

12. The high-speed data receiver of claim 11 , wherein the test data includes 8-bit serial data “01010101”.

13. The high-speed data receiver of claim 11 , wherein the deskew synchronous code includes 8-bit serial data “11111111”.

14. The high-speed data receiver of claim 13 , wherein the receiver is configured to receive differential signals as the normal data.

15. The high-speed data receiver of claim 9 , wherein the receiver is configured to initiate a deskew calibration operation upon detection of the deskew synchronous code.

16. The high-speed data receiver of claim 15 , wherein the receiver is configured to perform the deskew calibration operation during at least one of a plurality of vertical blanking periods.

17. An application processor comprising:
a transmitter D-PHY module configured to transmit a first deskew synchronous code through a first channel and to transmit a first clock signal through a first clock channel; and
a receiver D-PHY module configured to receive a second deskew synchronous code through a second channel and to receive a second clock signal through a second clock channel,
wherein the first deskew synchronous code is a sequence of all 1s.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Han Soo
• Kim Sung Jun
• Kim Chae Ryung
• Park Dong Uk
• Chung Youn Woong
• Choi Jung Myung
• Lim Han Kyul
• Cha Gyeong Han

Classifications

• H03K2005/00058

  controlled by a digital setting · CPC title

• H04L7/0041 Primary

  Delay of data signal · CPC title

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title