Pulse amplitude modulation (PAM) data communication with forward error correction

Patent metadata

Field	Value
Publication number	US-9564990-B1
Application number	US-201414304635-A
Country	US
Kind code	B1
Filing date	Jun 13, 2014
Priority date	Oct 16, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

The present invention is directed to data communication system and methods. More specifically, embodiments of the present invention provide an apparatus that receives data from multiple lanes, which are then synchronized for transcoding and encoding. A pseudo random bit sequence checker may be coupled to each of the plurality of lanes, which is configured to a first clock signal A. Additionally, an apparatus may include a plurality of skew compensator modules. Each of the skew compensator modules may be coupled to at least one of the plurality of lanes. The skew-compensator modules are configured to synchronize data from the plurality of lanes. The apparatus additionally includes a plurality of de-skew FIFO modules. Each of the de-skew compensator modules may be coupled to at least one of the plurality of skew compensator modules.

First claim

What is claimed is:

1. An apparatus for operating 25 Gigabit (25G), 40 Gigabit (40G), 50 Gigabit (50G), or 100 Gigabit (100G) signals in a communication network, the apparatus comprising:
a first plurality of bus lanes configured to receive an encoded and decoded 25G, 40G, 50G, or 100G signals;
a pseudo random bit sequence (PRBS) checker coupled to each of the first plurality of bus lanes, and configured to receive a first clock signal A;
a plurality of skew compensator modules, each of the skew compensator modules coupled to at least one of the plurality of first plurality of bus lanes;
a plurality of de-skew compensator modules, each of the de-skew compensator modules coupled to at least one of the plurality of skew compensator modules;
a first bus coupled to an output of each of the de-skew compensator modules, the first bus comprising a first output;
a clock rate converter device coupled to the first output of first bus, and configured to receive a second clock signal B;
a second bus coupled to an output of the clock rate converter module device;
a transcoder module coupled to an output of the second bus, and configured to receive a third clock rate C;
a third bus coupled to an output of the transcoder module;
a forward error correction (FEC) encoder module coupled to an output of the third bus, and configured to receive the third clock signal C;
a second plurality of bus lanes coupled to an output of the FEC encoder module;
a plurality of gear box modules coupled to the second plurality of bus lanes, each of the plurality of gear box modules is coupled to a pattern generator module;
a first MUX device coupled to a first output of a first gear box module out of a plurality of gear box modules;
a second MUX device coupled to a second output of the second gear box module out of the plurality of gear box modules;
a first gray mapping Pulse Amplitude Modulation (PAM) encoding module coupled to an output of the first MUX device; and
a second gray mapping PAM encoding module coupled to an output of the second MUX device.

2. The apparatus of claim 1 wherein the plurality of skew compensator modules is configured to provide a protocol lock Finite State Machine (FSM).

3. The apparatus of claim 1 wherein the plurality of skew compensator modules is configured to provide a block lock Finite State Machine (FSM).

4. The apparatus of claim 1 wherein the plurality of skew compensator modules is configured to detect alignment using one or more markers.

5. The apparatus of claim 1 wherein the plurality of de-skew FIFO modules accounts for skew variation.

6. The apparatus of claim 1 further comprising a control module for re-arranging an order of the plurality of lanes.

7. The apparatus of claim 6 wherein the control module comprises a BER monitor.

8. The apparatus of claim 1 wherein the gear boxes are configured to divide a first streaming into two streams.

9. The apparatus of claim 1 wherein the plurality of lanes are configured for 25G using at least one of the plurality of lanes, or configured for 40G using at least four of the plurality of lanes, each of which is configured at 10G, or configured for 100G using at least four of the plurality of lanes, each if which is configured at 25G, or configured for 50G using at least two of the plurality of lanes, each of which is configured at 25G.

10. The apparatus of claim 1 wherein each of the plurality of skew compensator modules comprises a protocol locking device Finite State Machine (FSM).

11. The apparatus of claim 1 wherein each of the first gray mapping PAM encoding module and the second gray mapping PAM encoding module is characterized by a PAM 4 code.

12. The apparatus of claim 11 further comprising a monitoring module configured to sense a signal to noise information to determine whether to initiate transfer of either the 25G, 40G, 50G, or 100G configuration using the PAM4 code.

13. The apparatus of claim 1 wherein the pre-coder module is configured to provide for a PHY (Physical Layer) support, SMF (Single Mode Fiber) support, or MMF (Multi-mode Fiber) support on a silicon photonics modulator.

14. The apparatus of claim 1 wherein the FEC encoder module is configured for BCH coding.

15. The apparatus of claim 1 further comprising a silicon photonics device coupled to the first gray mapping PAM encoding module coupled to the output of the first MUX device; and the second gray mapping PAM encoding module coupled to the output of the second MUX device, the silicon photonics device being coupled to at least one fiber configured in an optical network.

16. The apparatus of claim 15 wherein the optical network is provided in a data center.

17. The apparatus of claim 1 further comprising a trans-impedance amplifier coupled to an optical receiver and a decoding module.

18. A method for operating 25 Gigabit (25G), 40 Gigabit (40G), 50 Gigabit (50G), or 100 Gigabit (100G) signals in a communication network, the method comprising:
receiving data signals from a plurality of lanes, the plurality of lanes being characterized by an order and a data rate of 25G, 40G, and/or 100G;
performing error checking for the plurality of lanes at a first clock rate using a pseudo random bit sequence checker;
synchronizing the plurality of lanes with skew compensation and/or data alignment by mapping to a plurality of virtual lanes;
reordering the order of the plurality of virtual lanes based upon alignment markers at a second clock rate, wherein the alignment markers are not split between different virtual lanes based upon alignment markers;
transcoding data signals of the plurality of virtual lanes at a third clock rate;
performing forward error correction for the transcoded data signals at the third clock rate using a forward error correction encoder;
generating patterns based on the forward error correction for the transcoded data signals; and
mapping the patterns.

19. The method of claim 18 wherein the plurality of lanes are characterized by different data rates.

20. The method of claim 18 further comprising performing protocol locking for block synchronization.

Assignees

• Inphi Corp

Inventors

• Tiruvur Arun
• Riani Jamal
• Bhoja Sudeep

Classifications

• H04L27/04 Primary

  Modulator circuits; Transmitter circuits · CPC title

• H04L1/0041 Primary

  Arrangements at the transmitter end · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L1/0042

  Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence) · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title