Method, apparatus and system for deskewing parallel interface links

Patent metadata

Field	Value
Publication number	US-9832006-B1
Application number	US-201615162884-A
Country	US
Kind code	B1
Filing date	May 24, 2016
Priority date	May 24, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a clock channel to receive and distribute a clock signal to a plurality of data channels;
the plurality of data channels, wherein each of the plurality of data channels includes:
a first sampler to sample data;
a second sampler to sample the data; and
a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel;

a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels, wherein the plurality of data channels further comprises:
a first delay adjuster to receive the global calibration signal and adjust a phase of the clock signal based thereon;
a second delay adjuster to receive the local calibration signal and adjust a phase of at least one of a first sampling clock signal and a second sampling clock signal based thereon, wherein the first sampler is to sample the data according to the first sampling clock signal and the second sampler is to sample the data according to the second sampling clock signal;
a first buffer to receive the phase adjusted clock signal from the first delay adjuster and provide the phase adjusted clock signal to the second delay adjuster; and
a second buffer to receive the phase adjusted clock signal from the first delay adjuster and provide the phase adjusted clock signal to the second delay adjuster, out of phase from the phase adjusted clock signal provided by the first buffer.

2. The apparatus of claim 1 , wherein the deskew calibration circuit is to generate the local calibration signal based at least in part on a duty cycle between the first sampling clock signal and the second sampling clock signal.

3. The apparatus of claim 1 , wherein the global deskew calibration circuit is to dynamically and automatically generate the global calibration signal during a periodic calibration routine.

4. The apparatus of claim 3 , wherein the clock channel is to distribute the clock signal according to a calibration clock signal generated in the clock channel during the calibration routine.

5. The apparatus of claim 4 , wherein the global deskew calibration circuit is to provide a predetermined data sequence to the plurality of channels during the calibration routine.

6. The apparatus of claim 1 , wherein the global deskew calibration circuit is to generate and provide an independent global calibration signal to each of the plurality of data channels.

7. The apparatus of claim 1 , wherein the deskew calibration circuit of each of the plurality of data channels is to execute independently, responsive to initiation by the global deskew calibration circuit.

8. The apparatus of claim 1 , wherein the apparatus comprises a receiver to receive source synchronous multi-lane parallel data from a transmitter.

9. A system comprising:
a transmitter to send information including data and a clock signal via a plurality of parallel links; and
a receiver coupled to the transmitter to receive the information, the receiver comprising:
a clock channel to receive and distribute the clock signal to a plurality of data channels;
the plurality of data channels, wherein each of the plurality of data channels includes:
a first sampler to sample at least some of the data; and
a second sampler to sample the at least some of the data;

a first circuit to receive the clock signal from the clock channel, receive the data sampled by the first sampler and the data sampled by the second sampler from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels, wherein at least some of the plurality of data channels further comprises:
a second circuit to receive first sampled test data from the first sampler and second sampled test data from the second sampler and generate a local calibration signal;
a first delay adjuster to receive the global calibration signal and adjust a phase of the clock signal based thereon;
a first buffer to receive the phase adjusted clock signal from the first delay adjuster;
a second buffer to receive the phase adjusted clock signal from the first delay adjuster; and
a second delay adjuster coupled to the first buffer and the second buffer, the second delay adjuster to receive an output of the first buffer and the second buffer, and the local calibration signal and adjust a phase of at least one of a first sampling clock signal to clock the first sampler and a second sampling clock signal to clock the second sampler.

10. The system of claim 9 , wherein the system comprises a multi-chip module including a first semiconductor die having the transmitter and a second semiconductor die having the receiver.

Assignees

• Intel Corp

Inventors

• Bandi Chenchu Punnarao
• Srivastava Amit Kumar

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H04L7/041

  using special codes as synchronising signal · CPC title

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0091

  Transmitter details · CPC title