Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10312289-B1
Application number	US-201816040671-A
Country	US
Kind code	B1
Filing date	Jul 20, 2018
Priority date	Mar 19, 2018
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A semiconductor memory device comprises a substrate, a plurality of first wirings arranged in a first direction crossing a surface of the substrate, a second wiring extending in the first direction, a variable resistance film provided between the first wiring and the second wiring, a third wiring extending in a second direction crossing the first direction, a select transistor provided between an end of the second wiring and the third wiring. In addition, the semiconductor memory device comprises a chalcogen layer provided at at least a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate;
a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
a second wiring extending in the first direction;
a variable resistance film provided between the first wiring and the second wiring;
a third wiring extending in a second direction crossing the first direction;
a select transistor provided between an end of the second wiring and the third wiring; and
a chalcogen layer provided at at least one of a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor, wherein
the select transistor comprises:
a semiconductor layer being connected to the second wiring or the third wiring, and including:
a first semiconductor region;
a second semiconductor region between the first semiconductor region and the chalcogen layer; and
a third semiconductor region between the first and second semiconductor regions; and

a gate electrode facing the third semiconductor region.

2. The semiconductor memory device according to claim 1 , wherein
the first and second semiconductor regions include impurities of a first conductivity type,
the third semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

3. A semiconductor memory device comprising:
a substrate;
a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
a second wiring extending in the first direction;
a variable resistance film provided between the first wiring and the second wiring;
a third wiring extending in a second direction crossing the first direction;
a select transistor provided between an end of the second wiring and the third wiring; and
a chalcogen layer provided at at least one of a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor, wherein
the select transistor comprises:
a semiconductor layer being connected to the second wiring or the third wiring, and including:
a first semiconductor region; and
a second semiconductor region between the first semiconductor region and the chalcogen layer; and

a gate electrode facing the second semiconductor region, and
the chalcogen layer is connected to the second semiconductor region.

4. The semiconductor memory device according to claim 3 , wherein
the first semiconductor region includes impurities of a first conductivity type,
the second semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

5. A semiconductor memory device comprising:
a substrate;
a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
a second wiring extending in the first direction;
a variable resistance film provided between the first wiring and the second wiring;
a third wiring extending in a second direction crossing the first direction;
a select transistor connected to the third wiring; and
a chalcogen layer connected to the select transistor and the second wiring, wherein
the select transistor comprises:
a semiconductor layer including one end connected to the third wiring, and, the other end connected to the chalcogen layer; and
a gate electrode facing the semiconductor layer in the second direction.

6. The semiconductor memory device according to claim 5 , wherein
the semiconductor layer comprises:
a first semiconductor region;
a second semiconductor region between the first semiconductor region and the chalcogen layer; and
a third semiconductor region between the first and second semiconductor regions, and
the gate electrode faces the third semiconductor region.

7. The semiconductor memory device according to claim 6 , wherein
the first and second semiconductor regions include impurities of a first conductivity type,
the third semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

8. The semiconductor memory device according to claim 5 , wherein
the semiconductor layer comprises:
a first semiconductor region; and
a second semiconductor region between the first semiconductor region and the chalcogen layer,
the gate electrode faces the second semiconductor region, and
the chalcogen layer is connected to the second semiconductor region.

9. The semiconductor memory device according to claim 8 , wherein
the first semiconductor region includes impurities of a first conductivity type,
the second semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

Assignees

• Toshiba Memory Corp

Inventors

• Ota Kensuke
• Saitoh Masumi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C2013/009

  Write using potential difference applied between cell electrodes · CPC title

• G11C2213/15

  Current-voltage curve · CPC title