Processor using a level 3 translation lookaside buffer implemented in off-chip or die-stacked dynamic random-access memory

Patent metadata

Field	Value
Publication number	US-10296465-B2
Application number	US-201715654828-A
Country	US
Kind code	B2
Filing date	Jul 20, 2017
Priority date	Nov 29, 2016
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A processor architecture utilizing a L3 translation lookaside buffer (TLB) to reduce page walks. The processor includes multiple cores, where each core includes a L1 TLB and a L2 TLB. The processor further includes a L3 TLB that is shared across the processor cores, where the L3 TLB is implemented in off-chip or die-stack dynamic random-access memory. Furthermore, the processor includes a page table connected to the L3 TLB, where the page table stores a mapping between virtual addresses and physical addresses. In such an architecture, by having the L3 TLB with a very large capacity, performance may be improved, such as execution time, by eliminating page walks, which requires multiple data accesses.

First claim

The invention claimed is:

1. A processor, comprising:
a first processor core comprising:
a first level translation lookaside buffer; and
a second level translation lookaside buffer;

a second processor core comprising:
a first level translation lookaside buffer; and
a second level translation lookaside buffer;

a third level translation lookaside buffer connected to said first and second processor cores, wherein said third level translation lookaside buffer is shared across said first and second processor cores, wherein said third level translation lookaside buffer is implemented in memory or a storage device, wherein said first, second and third level translation lookaside buffers store recent translations of virtual memory to physical memory;
a page table connected to said third level translation lookaside buffer, wherein said page table stores a mapping between virtual addresses and physical addresses;
a first and a second second level data cache connected to said first and second processor cores; and
a third level data cache connected to said first and second second level data caches;
wherein said third level translation lookaside buffer is mapped into a memory address space, wherein said third level translation lookaside buffer is addressable, wherein said processor is configured to cache said third level translation lookaside buffer entries in said first and second second level data caches and said third level data cache.

2. The processor as recited in claim 1 , wherein said memory or said storage device comprises a dynamic random-access memory, wherein said dynamic random-access memory comprises a plurality of banks, wherein each of said plurality of banks comprises a row, wherein said row houses multiple translation lookaside buffer entries, wherein each of said translation lookaside buffer entries comprises a valid bit, a process identifier, a virtual address and a physical address.

3. The processor as recited in claim 2 , wherein each of said translation lookaside buffer entries further comprises a virtual machine identifier.

4. The processor as recited in claim 1 , wherein said third level translation lookaside buffer is implemented as a four way associative structure.

5. The processor as recited in claim 1 further comprising:
a first history counter predictor connected to said first processor core; and
a second history counter predictor connected to said second processor core;
wherein said first and second history counter predictors are configured to track a history of hits to said third level translation lookaside buffer.

6. The processor as recited in claim 5 , wherein said first and second history counter predictors are indexed using a portion of a virtual address.

7. The processor as recited in claim 6 , wherein said first and second history counter predictors use a three bit saturating counter per predictor entry.

8. The processor as recited in claim 7 , wherein said first and second history counter predictors are incremented in response to a hit to said third level translation lookaside buffer and are decremented in response to a miss to said third level translation lookaside buffer.

9. The processor as recited in claim 8 , wherein said first and second history counter predictors speculate a hit to said third level translation lookaside buffer in response to a counter value exceeding a threshold value.

10. The processor as recited in claim 8 , wherein said first and second history counter predictors speculate a miss to said third level translation lookaside buffer in response to a counter value not exceeding a threshold value.

11. The processor as recited in claim 1 further comprising:
a first and a second predictor connected to said first and second processor cores and said third level translation lookaside buffer, wherein said first and second predictors comprise two-bit entries, wherein a first of said two-bits is used to predict whether to bypass said first and second second level data caches and said third level data cache.

12. The processor as recited in claim 11 , wherein a second of said two-bits is used to predict a page size.

13. The processor as recited in claim 1 , wherein said third level translation lookaside buffer is implemented in off-chip or die-stack dynamic random-access memory.

14. The processor as recited in claim 1 , wherein said third level translation lookaside buffer is implemented in one of the following: phase-change memory and non-volatile random-access memory.

15. A processor, comprising:
a processor core comprising:
a first level translation lookaside buffer; and
a second level translation lookaside buffer;

a third level translation lookaside buffer connected to said processor core, wherein said third level translation lookaside buffer is implemented in memory or a storage device, wherein said first, second and third level translation lookaside buffers store recent translations of virtual memory to physical memory;
a page table connected to said third level translation lookaside buffer, wherein said page table stores a mapping between virtual addresses and physical addresses;
a first and a second second level data cache connected to said processor core; and
a third level data cache connected to said first and second second level data caches;
wherein said third level translation lookaside buffer is mapped into a memory address space, wherein said third level translation lookaside buffer is addressable, wherein said processor is configured to cache said third level translation lookaside buffer entries in said first and second second level data caches and said third level data cache.

16. The processor as recited in claim 15 , wherein said memory or said storage device comprises a dynamic random-access memory, wherein said dynamic random-access memory comprises a plurality of banks, wherein each of said plurality of banks comprises a row, wherein said row houses multiple translation lookaside buffer entries, wherein each of said translation lookaside buffer entries comprises a valid bit, a process identifier, a virtual address and a physical address.

17. The processor as recited in claim 16 , wherein each of said translation lookaside buffer entries further comprises a virtual machine identifier.

18. The processor as recited in claim 15 , wherein said third level translation lookaside buffer is implemented as a four way associative structure.

19. The processor as recited in claim 15 , wherein said third level translation lookaside buffer is implemented in off-chip or die-stack dynamic random-access memory.

20. The processor as recited in claim 15 , wherein said third level translation lookaside buffer is implemented in one of the following: phase-change memory and non-volatile random-access memory.

Assignees

• Univ Texas

Inventors

• John Lizy K
• Ryoo Jee Ho
• Gulur Nagendra

Classifications

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F12/1054

  the data cache being concurrently physically addressed · CPC title

• G06F12/1063 Primary

  the data cache being concurrently virtually addressed · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title