Data processing apparatus, and a method of handling address translation within a data processing apparatus

Patent metadata

Field	Value
Publication number	US-10133675-B2
Application number	US-201515325250-A
Country	US
Kind code	B2
Filing date	Jun 22, 2015
Priority date	Jul 29, 2014
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.

First claim

The invention claimed is:

1. A data processing apparatus comprising:
processing circuitry configured to issue a memory access request specifying a virtual address for a data item;
address translation circuitry configured to perform an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item, the address translation circuitry including page table walk circuitry configured to generate at least one memory page table walk request in order to retrieve the at least one descriptor required for the address translation process;
walk ahead circuitry located in a path between the address translation circuitry and a memory device containing the at least one page table, the walk ahead circuitry comprising:
detection circuitry configured to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table; and
further request generation circuitry configured to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request, wherein:

the page table walk circuitry is configured to include, within the detected memory page table walk request, additional information not required to retrieve the descriptor requested by that detected memory page table walk request; and
the further request generation circuitry is configured to use said additional information when generating said prefetch memory request.

2. A data processing apparatus as claimed in claim 1 , wherein the data prefetched from the memory device in response to the prefetch memory request is one of the data item required by the modified memory access request and a further descriptor required by the address translation process.

3. A data processing apparatus as claimed in claim 1 , wherein:
the page table walk circuitry is configured to use a portion of the virtual address in order to determine a descriptor address, and to include within the detected page table walk request said descriptor address; and
the page table walk circuitry is further configured to include, as said additional information, a further portion of the virtual address.

4. A data processing apparatus as claimed in claim 1 , wherein:
the address translation circuitry is configured to perform, as the address translation process, a multi-level address translation process with reference to descriptors provided by a plurality of page tables configured in multiple hierarchical levels, and the page table walk circuitry is configured to generate memory page table walk requests in order to retrieve the descriptors required for the multi-level address translation process;
the memory page table walk request detected by the detection circuitry is for a descriptor in a page table at one hierarchical level; and
the further request generation circuitry is configured to generate as the prefetch memory request, for each of at least one subsequent hierarchical level, a prefetch memory page table walk request in order to prefetch an associated descriptor in a page table at that subsequent hierarchical level.

5. A data processing apparatus as claimed in claim 4 , wherein:
the further request generation circuitry is configured to determine a descriptor address for the associated descriptor in a page table at a first subsequent hierarchical level with reference to said further portion of the virtual address and the descriptor retrieved as a result of the memory device processing the detected memory page table walk request; and
the further request generation circuitry is further configured to include the determined descriptor address within the generated prefetch memory page table walk request for said first subsequent hierarchical level.

6. A data processing apparatus as claimed in claim 5 , wherein for each additional subsequent hierarchical level, the further request generation circuitry is configured to determine a descriptor address for the associated descriptor in a page table at that additional subsequent hierarchical level with reference to said further portion of the virtual address and the descriptor obtained as a result of the memory device processing the prefetch memory page table walk request for a preceding subsequent hierarchical level.

7. A data processing apparatus as claimed in claim 4 , wherein:
the further request generation circuitry is configured to generate, for each of multiple subsequent hierarchical levels, a prefetch memory page table walk request; and
the page table walk circuitry is further configured to include within the detected page table walk request, level indication data used by the further request generation circuitry to determine which bits of the further portion of the virtual address to use when generating the prefetch memory page table walk request at each of the multiple subsequent hierarchical levels.

8. A data processing apparatus as claimed in claim 4 , wherein said at least one subsequent hierarchical level includes a final hierarchical level, and the further request generation circuitry is further configured to generate a prefetch modified memory access request specifying a physical address for the data item in order to prefetch the data item.

9. A data processing apparatus as claimed in claim 4 , wherein the walk ahead circuitry further includes a walk ahead storage structure configured to store the associated descriptor retrieved from the memory device as a result of each prefetch memory page table walk request.

10. A data processing apparatus as claimed in claim 9 , wherein the walk ahead storage structure is further configured to store the prefetched data item retrieved from the memory device as a result of the prefetch modified memory access request.

11. A data processing apparatus as claimed in claim 9 , wherein the walk ahead storage structure is configured as a cache.

12. A data processing apparatus as claimed in claim 4 , wherein the walk ahead circuitry is configured to be responsive to control information to determine the number of subsequent hierarchical levels for which associated descriptors are prefetched ahead of a current hierarchical level for which the page table walk circuitry has generated a memory page table walk request.

13. A data processing apparatus as claimed in claim 1 , wherein the walk ahead circuitry is provided within a memory controller associated with the memory device.

14. A data processing apparatus as claimed in claim 13 , wherein the walk ahead circuitry is configured to re-use at least one existing component of the memory controller.

15. A data processing apparatus as claimed in claim 14 , wherein the walk ahead storage structure is provided by a read data queue within the memory controller.

16. A data processing apparatus as claimed in claim 4 , wherein a descriptor provided in a page table at one hierarchical level provides a base address for a page table in a subsequent hierarchical level.

17. A data processing apparatus as claimed in claim 4 , wherein a descriptor provided in a page table at a final hierarchical level provides a base address for a memory page containing the data item associated with the virtual address specified in the memory access request.

18. A data processing apparatus as claimed in claim 1 wherein the page table walk circuitry is configured to include, within the detected memory

Assignees

• Advanced Risc Mach Ltd

Inventors

• Hansson Andreas
• Saidi Ali
• Udipi Aniruddha Nagendran
• Diestelhorst Stephan

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/654

  Look-ahead translation · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title