Memory system

Patent metadata

Field	Value
Publication number	US-2016275017-A1
Application number	US-201615067558-A
Country	US
Kind code	A1
Filing date	Mar 11, 2016
Priority date	Mar 20, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

First claim

1 . A memory system comprising:
a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory; a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address; and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

2 . The memory system according to claim 1 ,
wherein the first cache memory which has a set associative structure comprising a plurality of ways or a full associative structure comprising a plurality of ways, each way including memory regions with an equal size, and the first control circuitry stores the address conversion information stored in the first translation lookaside buffer in at least one of the plurality of ways during the power off.

3 . The memory system according to claim 2 ,
wherein the first cache memory has a set associative structure comprising the plurality of ways and a plurality of sets, and the first control circuitry uses all of the sets in one or more ways among the plurality of ways to store the address conversion information in the first translation lookaside buffer during the power off.

4 . The memory system according to claim 2 ,
wherein the first control circuitry gives priority to each way and uses each way to store the address conversion information in ascending order of the priority during the power off.

5 . The memory system according to claim 2 , further comprising:
a second control circuitry that controls the first cache memory, wherein the second control circuitry controls whether to use each of the plurality of ways as the first cache memory and manages a way to be used as the first cache memory and a way which stores the address conversion information stored in the first translation lookaside buffer during the power off.

6 . The memory system according to claim 5 ,
wherein the second control circuitry comprises a register that is incremented according to the number of ways used as the first cache memory and is decremented according to the number of ways storing the address conversion information, or a register that is decremented according to the number of ways used as the first cache memory and is incremented according to the number of ways storing the address conversion information.

7 . The memory system according to claim 5 ,
wherein the first control circuitry requests the second control circuitry to invalidate at least one of cache regions of the first cache memory during the power off, the second control circuitry writes data, which is present in the cache region to be invalidated and is not written to a lower-level memory that is at a lower level than the first cache memory, to the lower-level memory, invalidates the cache region after the writing to the lower-level memory is completed, and notifies the first control circuitry that the cache region is invalidated, and the first control circuitry stores the address conversion information stored in the first translation lookaside buffer in the invalidated cache region.

8 . The memory system according to claim 1 ,
wherein the first control circuitry writes all of the address conversion information stored in the invalidated cache region to the first translation lookaside buffer when power is turned on again, the first control circuitry notifies the second control circuitry that the writing of the address conversion information to the first translation lookaside buffer is completed, and the second cache control circuitry uses the invalidated cache region as the first cache memory.

9 . A memory system comprising:
a non-volatile memory; a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address; and a first control circuitry that determines whether to use the non-volatile memory as a first cache memory which can be accessed at a higher speed than a main memory or as a second translation lookaside buffer which has a lower access priority than the first translation lookaside buffer.

10 . The memory system according to claim 9 ,
wherein the non-volatile memory has a set associative structure comprising a plurality of ways or a full associative structure comprising a plurality of ways and comprises a plurality of ways including memory regions with an equal size, and the first control circuitry determines whether to use at least one of the plurality of ways as the second translation lookaside buffer.

11 . The memory system according to claim 10 ,
wherein the non-volatile memory has a set associative structure comprising the plurality of ways and a plurality of sets, and when the first control circuitry determines that the non-volatile memory is used as the second translation lookaside buffer, the first control circuitry uses all of the sets in one or more ways among the plurality of ways to store the address conversion information in the second translation lookaside buffer during the power off,

12 . The memory system according to claim 10 ,
wherein the first control circuitry gives priority to each way and uses the way to store the address conversion information in ascending order of the priority during the power off.

13 . The memory system according to claim 10 , further comprising:
a second control circuitry that controls the first cache memory, wherein the second control circuitry controls whether to use each way as the first cache memory and manages a way which is used as the first cache memory and a way which stores the address conversion information stored in the first translation lookaside buffer during the power off.

14 . The memory system according to claim 13 ,
wherein the second control circuitry comprises a register that is incremented according to the number of ways used as the first cache memory and is decremented according to the number of ways storing the address conversion information, or a register that is decremented according to the number of ways used as the first cache memory and is incremented according to the number of ways storing the address conversion information.

15 . The memory system according to claim 10 , further comprising:
a second control circuitry that controls the first cache memory; and a third control circuitry that controls the second translation lookaside buffer, wherein the first control circuitry requests the second control circuitry to write data, which is not written to a lower-level memory among data stored in at least one of cache regions of the first cache memory, to the lower-level memory, the second control circuitry writes the data in the cache region to the lower-level memory in response to the request and notifies the first control circuitry that the writing is completed, the first control circuitry requests the third control circuitry to initialize the cache region, the third control circuitry initializes the cache region, notifies the first control circuitry that initialization is completed, and controls the cache region as the second translation lookaside buffer, and the first control circuitry uses the cache region as the second translation lookaside buffer.

16 . The memory system according to claim 10 , further comprising:
a second control circuitry that controls the first cache memory, wherein the first control circuitry requests the second control circuitry to initialize the region used as the secon

Assignees

• Toshiba Kk
• Toshiba Kk

Inventors

• Takeda Susumu

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title