Vertical NAND device with low capacitance and silicided word lines

Patent metadata

Field	Value
Publication number	US-9449984-B2
Application number	US-201414465099-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Apr 10, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.

First claim

What is claimed is:

1. A completed three dimensional memory device, comprising:
a substrate;
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate;
at least one charge storage region located adjacent to semiconductor channel; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
wherein each of the plurality of control gate electrodes comprises:
a semiconductor material portion consisting essentially of a p-doped or n-doped Group IV semiconductor material; and
a metal silicide portion composed of a metal silicide of the Group IV semiconductor material and at least one metal,

wherein surfaces of the semiconductor material portion are in contact with the metal silicide portion and the at least one charge storage region,
wherein each vertically neighboring pair of control gate electrodes is spaced by a respective air gap that extends parallel to the major surface of the substrate and is in physical contact with substantially horizontal surfaces of an overlying metal silicide portion and an underlying metal silicide portion
wherein a vertically extending volume extending through the plurality of control gate electrodes is adjoined to the air gaps which comprise a plurality of laterally extending volumes located between each vertically neighboring pair of control gate electrodes to provide a contiguous air gap comprising a single undivided space.

2. The device of claim 1 , wherein:
a first edge surface of each of the plurality of control gate electrodes comprises an edge surface of the semiconductor material portion which contacts the at least one charge storage region;
a second edge surface, a top surface, and a bottom surface of each of the plurality of control gate electrodes are not in contact with the at least one charge storage region; and
the first edge surface and the second edge surface of the plurality of control gate electrodes are positioned substantially perpendicular to the major surface of the substrate.

3. The device of claim 1 , wherein:
the semiconductor channel has a pillar shape having a solid or hollow circular cross section when viewed from above; and
the entire pillar-shaped semiconductor channel and the entire at least one charge storage region extend substantially perpendicular to the major surface of the substrate.

4. The device of claim 1 , wherein:
the device comprises a vertical NAND device is located over the substrate;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three dimensional NAND strings over the silicon substrate;
at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

5. The device of claim 1 , wherein the contiguous air gap extends to a region located above a horizontal plane including a topmost surface of the plurality of control gate electrodes.

6. The device of claim 1 , further comprising a support mask located above the plurality of control gate electrodes, wherein a top surface of the contiguous air gap is a bottom surface of the support mask.

7. The device of claim 6 , wherein the support mask is patterned layer including at least one opening therein.

8. A three dimensional memory device, comprising:
a substrate;
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate;
at least one charge storage region located adjacent to semiconductor channel; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
wherein each of the plurality of control gate electrodes comprises:
a semiconductor material portion composed of a Group IV semiconductor material; and
a metal silicide portion composed of a metal silicide of the Group IV semiconductor material and at least one metal, wherein surfaces of the semiconductor material portion are in contact with the metal silicide portion and the at least one charge storage region,

wherein each vertically neighboring pair of control gate electrodes is spaced by a respective air gap that extends parallel to the major surface of the substrate, and
wherein a vertically extending volume extending through the plurality of control gate electrodes is adjoined to the air gaps to provide a contiguous air gap;
further comprising a support mask located above the plurality of control gate electrodes, wherein a top surface of the contiguous air gap is a bottom surface of the support mask, wherein the support mask is patterned layer including at least one opening therein; and
further comprising a plurality of memory cells embedded within the plurality of control gate electrodes, wherein:
a first subset of the plurality of memory cells is located underneath a portion of the support mask; and
a second subset of the plurality of memory cells is located underneath the at least one opening in the support mask.

9. The device of claim 8 , wherein the contiguous air gap vertically extends up to a horizontal plane including a topmost surface the plurality of memory cells.

10. A three dimensional memory device, comprising:
a substrate;
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate;
at least one charge storage region located adjacent to semiconductor channel; and
a plurality of control gate electrodes having a strip share extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
wherein each of the plurality of control gate electrodes comprises:
a semiconductor material portion composed of a Group IV semiconductor material; and
a metal silicide portion composed of a metal silicide of the Group IV semiconductor material and at least one metal, wherein surfaces of the semiconductor material portion are in contact with the metal silicide portion and the at least one charge storage region,

wherein each vertically neighboring pair of control gate electrodes is spaced by a respective air gap that extends parallel to the major surface of the substrate, and
wherein a vertically extending volume extending through the plurality of control gate electrodes is adjoined to the air gaps to provide a contiguous air gap;
further comprising a support mask located above the pluralit

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Alsmeier Johann
• Rabkin Peter

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D64/683

  being parallel to the channel plane · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title