Three-dimensional memory device containing floating gate select transistor

Patent metadata

Field	Value
Publication number	US-10290643-B1
Application number	US-201815876884-A
Country	US
Kind code	B1
Filing date	Jan 22, 2018
Priority date	Jan 22, 2018
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and control gate electrodes located over a substrate, a drain select gate device located above the alternating stack, and a vertical semiconductor channel extending through the alternating stack and through the drain select gate device. The drain select gate device contains a floating gate electrode located between the vertical semiconductor channel and a first drain select gate electrode.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and control gate electrodes located over a substrate;
a drain select gate device located above the alternating stack; and
a vertical semiconductor channel extending through the alternating stack and through the drain select gate device,
wherein the drain select gate device comprises a floating gate electrode located between the vertical semiconductor channel and a first drain select gate electrode.

2. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises:
plural alternating stacks of the insulating layers and electrically conductive layers located over the substrate, wherein the electrically conductive layers comprise the control gate electrodes, the drain select gate electrode located over the control gate electrodes, and source select gate electrode located under the control gate electrodes;
memory stack structures extending through the plural alternating stacks, wherein each of the memory stack structures comprises floating gate electrodes laterally surrounding a respective vertical semiconductor channel and spaced from the electrically conductive layers by a respective blocking dielectric;
a first backside trench and a second backside trench vertically extending between a first alternating stack among the plural alternating stacks and a pair of neighboring alternating stacks adjacent to the first alternating stack; and
at least one dielectric isolation structure comprising a dielectric material embedded within the first alternating stack, and dividing a topmost electrically conductive layer within the first alternating stack into at least two discrete electrically isolated drain select gate electrodes comprising the first drain select gate electrode and a second drain select gate electrode.

3. The three-dimensional memory device of claim 2 , wherein:
a subset of the floating gate electrodes located at a level of the topmost electrically conductive layer directly contacts a respective sidewall of the at least one dielectric isolation structure;
a subset of the electrically conductive layers comprising the control gate electrodes within the first alternating stack continuously extend laterally from the first backside trench to the second backside trench; and
each of the at least two discrete electrically isolated drain select gate electrodes has a lateral extent that is less than one half of a lateral distance between the first backside trench and the second backside trench.

4. The three-dimensional memory device of claim 3 , wherein:
the first backside trench and the second backside trench laterally extend along a first horizontal direction;
the sidewalls of the at least one dielectric isolation structure that contact the subset of the floating gate electrodes laterally extend along the first horizontal direction; and
each of the sidewalls of the at least one dielectric isolation structure that contact the subset of the floating gate electrodes is within a respective two-dimensional plane.

5. The three-dimensional memory device of claim 3 , wherein each floating gate electrode within the subset of the floating gate electrodes directly contacting the respective sidewall of the at least one dielectric isolation structure is partially surrounded by a respective blocking dielectric including a pair of disjoined sidewalls that contact a respective one of the at least one dielectric isolation structure.

6. The three-dimensional memory device of claim 5 , wherein each floating gate electrode within the subset of the floating gate electrodes directly contacting the respective sidewall of the at least one dielectric isolation structure laterally surrounds a respective tunneling dielectric layer that does not directly contact, and is laterally spaced from, the at least one dielectric isolation structure.

7. The three-dimensional memory device of claim 3 , wherein the subset of the floating gate electrodes directly contacting the respective sidewall of the at least one dielectric isolation structure has a smaller horizontal cross-sectional area than another subset of the floating gate electrodes located at levels below the at least one dielectric isolation structure.

8. The three-dimensional memory device of claim 2 , wherein all of the memory stack structures extending through the first alternating stack are arranged as rows of memory stack structures having a same inter-row pitch throughout.

9. The three-dimensional memory device of claim 2 , wherein:
the first alternating stack comprises a terrace region in which each electrically conductive layer of the first alternating stack below the topmost electrically conductive layer within the first alternating stack laterally extends farther than an overlying electrically conductive layer within the first alternating stack;
the terrace region includes stepped surfaces of the first alternating stack that continuously extend from a bottommost layer within the first alternating stack to a topmost layer within the first alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

10. The three-dimensional memory device of claim 9 , wherein:
the first and second backside trenches and the at least one dielectric isolation structure laterally extend into the retro-stepped dielectric material portion; and
each of the at least two discrete electrically isolated drain select gate electrodes is contacted by different contact via structures.

11. The three-dimensional memory device of claim 2 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
a subset of the electrically conductive layers located below the at least two discrete electrically isolated drain select gate electrodes comprises, or is electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the control gate electrodes have a strip shape extending substantially parallel to the top surface of the substrate, and the control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Assignees

• Sandisk Technologies Llc

Inventors

• Kai James
• Alsmeier Johann
• Zhang Yanli
• Zhang Peng

Classifications

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic