Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof

Patent metadata

Field	Value
Publication number	US-9972641-B1
Application number	US-201615354795-A
Country	US
Kind code	B1
Filing date	Nov 17, 2016
Priority date	Nov 17, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
an isolation trench laterally extending along a horizontal direction and dividing a set of layers including at least two topmost electrically conductive layers within the alternating stack into two physically disjoined layer stacks including respective segments of the at least two topmost electrically conductive layers; and
two conductive rail structures located on lengthwise sidewalls of the isolation trench and laterally extending along the horizontal direction, wherein each of the two conductive rail structures is electrically shorted to segments of the at least two topmost electrically conductive layers located within a respective physically disjoined layer stack.

2. The three-dimensional memory device of claim 1 , further comprising a dielectric fill material portion located within the isolation trench and contacting widthwise sidewalls of the isolation trench and inner sidewalls of the two conductive rail structures.

3. The three-dimensional memory device of claim 1 , wherein each of the two conductive rail structures has a substantially uniform vertical cross-sectional shape that is invariant with lateral translation along the horizontal direction which is perpendicular to the lengthwise sidewalls of the isolation trench.

4. The three-dimensional memory device of claim 3 , wherein physical interfaces between the two conductive rail structures and the at least two topmost electrically conductive layers coincide with the lengthwise sidewalls of the isolation trench.

5. The three-dimensional memory device of claim 1 , wherein physical interfaces between the two conductive rail structures and the at least two topmost electrically conductive layers are laterally offset from the lengthwise sidewalls of the isolation trench along a direction perpendicular to the lengthwise direction.

6. The three-dimensional memory device of claim 1 , wherein each of the two conductive rail structures has a variable thickness that has local maxima at levels of the at least two topmost electrically conductive layers and has at least one local minimum at each level of an insulating layer within the set of layers including the at least two topmost electrically conductive layers.

7. The three-dimensional memory device of claim 6 , wherein the two conductive rail structures comprise a different conductive material than the electrically conductive layers.

8. The three-dimensional memory device of claim 1 , wherein a bottommost surface of the isolation trench is located within one of the insulating layers within the alternating stack.

9. The three-dimensional memory device of claim 1 , wherein:
a bottommost surface of the isolation trench is located within the substrate; and
a dielectric rail structure is located at a lower portion of the isolation trench, and contacts the substrate and bottom surfaces of the two conductive rail structures.

10. The three-dimensional memory device of claim 9 , wherein the dielectric rail structure comprises at least two different dielectric materials.

11. The three-dimensional memory device of claim 1 , wherein a semiconductor source region located at a bottom end of each vertical semiconductor channel is electrically shorted to a source electrode which comprises at least one bottommost electrically conductive layer within the alternating stack.

12. The three-dimensional memory device of claim 1 , further comprising:
a backside contact via structure vertically extending through the alternating stack;
an insulating spacer laterally surrounding the backside contact via structure and extending through the alternating stack; and
a source region located in the substrate and contacting a bottom surface of the backside contact via structure.

13. The three-dimensional memory device of claim 1 , wherein:
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

14. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

15. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are replaced with, electrically conductive layers;
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
forming an isolation trench laterally extending along a horizontal direction at least through a set of layers including at least two topmost spacer material layers within the alternating stack, wherein the isolation trench divides each layer within the set of layers into multiple segments; and
forming two conductive rail structures on lengthwise sidewalls of the isolation trench, wherein each of the two conductive rail structures is electrically shorted to segments of at least two topmost electrically conductive layers provided within a respective one of two physically disjoined layer stacks that are separated by the isolation trench.

16. The method of claim 15 , further c

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Liu Jin
• Makala Raghuveer S
• Chowdhury Murshed
• Alsmeier Johann

Classifications

• H10P50/264

  by chemical means · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title