Method of making a three-dimensional memory array with etch stop

Patent metadata

Field	Value
Publication number	US-9431409-B2
Application number	US-201314066788-A
Country	US
Kind code	B2
Filing date	Oct 30, 2013
Priority date	Aug 15, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.

First claim

What is claimed is:

1. A three dimensional memory device, comprising:
a substrate;
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate;
at least one charge storage region located adjacent to the semiconductor channel;
a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
an etch stop layer located between the substrate and the plurality of control gate electrodes;
a first insulating layer located between the etch stop layer and the substrate, or between the etch stop layer and the plurality of control gate electrodes;
a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a recessed surface of the etch stop layer; and
a material portion located in the trench and having a bottommost surface that contacts the top surface of the etch stop layer and continuously extending through the plurality of control gate electrodes and above a horizontal plane including a topmost surface of the plurality of control gate electrodes,

wherein the semiconductor channel extends through the etch stop layer and the first insulating layer.

2. The device of claim 1 , wherein:
the device comprises a vertical NAND string; and
the at least one charge storage region comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric which are located between the semiconductor channel and the plurality of control gate electrodes.

3. The device of claim 1 , wherein the insulating layer comprises silicon oxide and the etch stop layer comprises aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, silicon carbide or silicon carbonitride.

4. The device of claim 1 , further comprising a second insulating layer locate between the etch stop layer and the plurality of control gate electrodes.

5. The device of claim 1 , further comprising an air gap enclosed by the material portion and extending from below a horizontal plane including a bottommost surface of the plurality of control gate electrodes to a region above the horizontal plane including the topmost surface of the plurality of control gate electrodes.

6. The device of claim 5 , wherein the air gap laterally protrudes into portions between each vertically neighboring pair of control gate electrodes among the plurality of control gate electrodes.

7. The device of claim 5 , wherein the material portion comprises a silicide of a metal.

8. The device of claim 1 , wherein the material portion comprises a stoichiometric or non-stoichiometric dielectric material selected from AlO x , AlN, AlON, SiC, SiCN, TiN and TiO x , and fills the trench.

9. A three dimensional memory device, comprising:
a substrate;
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate;
at least one charge storage region located adjacent to the semiconductor channel;
a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
an etch stop layer located between the substrate and the plurality of control gate electrodes;
a first insulating layer located between the etch stop layer and the substrate, or between the etch stop layer and the plurality of control gate electrodes:
a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a recessed surface of the etch stop layer; and
a material portion located in the trench and having a bottommost surface that contacts the top surface of the etch stop layer and continuously extending through the plurality of control gate electrodes and above a horizontal plane including a topmost surface of the plurality of control gate electrodes,

wherein:
the device comprises a vertical NAND string;
the semiconductor channel has a U-shaped side cross section, comprising:
two wing portions which extend substantially perpendicular to the major surface of the substrate through the etch stop layer, and
a connecting portion which extends substantially parallel to the major surface of the substrate below the etch stop layer and which connects the two wing portions;

the connecting portion of the semiconductor channel is located below an air gap trench which separates the two wing portions; and
the connecting portion is located below the etch stop layer.

10. The device of claim 9 , further comprising an air gap enclosed by the material portion and extending from below a horizontal plane including a bottommost surface of the plurality of control gate electrodes to a region above the horizontal plane including the topmost surface of the plurality of control gate electrodes.

11. The device of claim 10 , wherein the air gap laterally protrudes into portions between each vertically neighboring pair of control gate electrodes among the plurality of control gate electrodes.

12. The device of claim 10 , wherein the material portion comprises a silicide of a metal.

13. The device of claim 9 , wherein the material portion comprises a stoichiometric or non-stoichiometric dielectric material selected from AlO x , AlN, AlON, SiC, SiCN, TiN and TiO x , and fills the trench.

14. A monolithic, three dimensional array of memory devices located over a silicon substrate, comprising an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level, wherein at least one vertically oriented NAND string of the array of vertically oriented NAND strings comprises:
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a silicon substrate;
at least one charge storage region located adjacent to the semiconductor channel;
a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the silicon substrate and below the first device level;
an etch stop layer located between the silicon substrate and the plurality of control gate electrodes;
a first insulating layer located between the etch stop layer and the silicon substrate, or between the etch stop layer and the plurality of control gate electrodes;
a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a rece

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lee Yao-Sheng
• Alsmeier Johann

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H01L27/11578

  Electricity · mapped topic